addressable.wiki
5.0 × 5.0 mm 4 pins top-emitting

APA104

5050 · smd · APA104 · APA Electronic

1-wire RGB 4–5.5 V active

Also sold as APA104, WS2812B compatible

At a glance

Colour
RGB8 bits per channel
Data
1-wiretimed pulses on one line
Supply
4–5.5 Vno backup data line
Size
5.0 × 5.0 × 1.6 mm4 pins · top
Max current
—per-channel not recorded
PWM
—reset 280 µs
Library support
FastLED WLED Adafruit

APA’s WS2812B workalike in the same 5050 footprint. Worth knowing about mainly because it ships inside strip sold as “WS2812B” without disclosure, and its reset requirements differ enough to matter on a marginal driver.

Current per channel and the maximum are left blank: no datasheet for this part is held, and the earlier 20 mA / 60 mA figures were a design rule of thumb rather than a sheet’s rating. A blank makes you check; a plausible wrong number does not. The 120 degree viewing angle was likewise unsourced and is blank.

Variants

One row per orderable SKU. Everything not listed is inherited from the part above.

Order codeFaceLensWhite PinsSiliconStatusFirst seenDatasheet
APA104 white clear — 4 — active unknown —

Pinout

APA104
APA104 5050 package, top and side viewPin 1 is ringed. pin 1 VDD (power), pin 2 DOUT (data out), pin 3 VSS (ground), pin 4 DIN (data in).11 VDDpower22 DOUTdata out33 VSSground44 DINdata in5.4 mm overall5.0 mmtop view1.6 mmside view
  • Power
  • Data
  • Ground
  • Pin 1
  • Cut corner

Outline drawn from the package family and the recorded dimensions; not yet checked against a datasheet. Pad sizes are approximate. No datasheet is held; pin order unverified. What this means.

  1. 1 VDD power
  2. 2 DOUT data out
  3. 3 VSS ground
  4. 4 DIN data in

Protocol — APA104

Timings shown from fastled.

APA104 bit timingAPA104 bit timing: a zero bit is 250 nanoseconds high then 1000 low; a one bit is 875 high then 375 low; reset 280 microseconds low1 · Bit encoding, to scaleDINhighlowbit 0 period 1250 nsbit 1 period 1250 nsT0H 250 nsT1H 875 nsT0L 1000 nsT1L 375 ns"0" bit"1" bit02505007501000125015001750200022502500time, ns2 · One frame: 24 bits, most-significant bit firstDIN170110010007100110101700101100bitG · 8 bitsR · 8 bitsB · 8 bitsWire order GRB · frame = 24 × ~1250 ns ≈ 30 µs · example data, first bits 1 0 1 …3 · RESET / latchlast bits of frame 1first bits of frame 2LEDs latch the data they receivedRESET: DIN low ≥ 280 µs (not to scale)4 · Cascade: each DOUT feeds the next DINMCULED 1DINDOUTLED 2DINDOUTLED NDINDOUTLED 1 keeps the first 24 bits, re-shapes the signal and sends the rest out on DOUT;LED 2 keeps the next 24, and so on. The last LED's DOUT is left unconnected.
T0H 250 / T0L 1000 · T1H 875 / T1L 375 ns · period 1250 ns · reset 280 µs source: fastled (driver-tuned, not the datasheet)

Compatibility

  • near clone WS2812B

    Same single-wire 800 kHz scheme and the same 5050 footprint, and every library drives it as a WS2812. Reset requirements differ, so a marginal driver that works on one may not work on the other.

  • near clone of this WS2812B

    Same 800 kHz single-wire signalling, but the APA104 inverts nothing and differs in reset requirements; usually interchangeable in practice.

Similar parts

Same protocol or package first, then the same data scheme and colour channels.

Was this page useful?

0 people found this useful