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Chongtian PT (4020 RGBIC) single-wire IC

1-wire RGB · Chongtian · chongtian

Channels
RGB
Bits / channel
8
Supply
3.5–5.5 V
PWM
—
Backup data
no
Packages
1

The 4020 version with its own feature list and a built-in fallback pattern; the sheet’s table is the 0.3 / 0.9 / 0.9 / 0.3 us set of chongtian-m but with an 80 us reset and RGB order, and the electrical page is a different template, so it is kept as a separate protocol rather than folded into chongtian-m.

Refresh & flicker

Chongtian describes it as an RGBIC LED with ‘internal MCU firmware, single- wire serial interface, data latch and constant-current drive’: 3.5-5.5 V, default output 12 mA, default off at power-up, 256 grey levels, 800 kbps, 50,000 h life, ‘when the signal input is cut off the LED plays a fixed seven-colour pattern in sync so downstream chips are not stopped’. Data order R, G, B, MSB first (note on the sheet: ‘in the order RGB’); the cascade figure is Trst + 24 bits x N + Trst.

Timing

Chongtian PT (4020 RGBIC) single-wire IC bit timingChongtian PT (4020 RGBIC) single-wire IC bit timing: a zero bit is 300 nanoseconds high then 900 low; a one bit is 900 high then 300 low; tolerance plus or minus 50 nanoseconds; reset 80 microseconds low1 · Bit encoding, to scaleDINhighlowbit 0 period 1200 nsbit 1 period 1200 nsT0H 300 ±50 nsT1H 900 ±50 nsT0L 900 ±50 nsT1L 300 ±50 ns"0" bit"1" bit020040060080010001200140016001800200022002400time, ns± tolerance on each falling edge2 · One frame: 24 bits, most-significant bit firstDIN170110010007100110101700101100bitch 1 · 8 bitsch 2 · 8 bitsch 3 · 8 bitsChannel order not recorded for this protocol · frame = 24 × ~1200 ns ≈ 28.8 µs · example data, first bits 1 0 1 …3 · RESET / latchlast bits of frame 1first bits of frame 2LEDs latch the data they receivedRESET: DIN low ≥ 80 µs (not to scale)4 · Cascade: each DOUT feeds the next DINMCULED 1DINDOUTLED 2DINDOUTLED NDINDOUTLED 1 keeps the first 24 bits, re-shapes the signal and sends the rest out on DOUT;LED 2 keeps the next 24, and so on. The last LED's DOUT is left unconnected.
T0H 300 / T0L 900 · T1H 900 / T1L 300 ns · ±50 ns · period 1200 ns · reset 80 µs source: datasheet
SourceT0HT0LT1HT1LPeriodRateReset±
datasheet ↗ 300 ns 900 ns 900 ns 300 ns 1200 ns 833 kHz 80 µs 50 ns
The 800 kHz transfer rate is tested at 67 percent duty (‘data 1’); DIN to DOUT delay 500 ns max (typ not given); Iout rise 70 ns, fall 100 ns at VDS 1.5 V, 12 mA.

Library support

Not checked against FastLED, Adafruit or WLED source.

Parts using this protocol

Dating evidence

Evidence, not a release date. A library commit proves the part existed by that date and says nothing about how long before.

  • 2026-01-23 datasheet revision Chongtian CT-4020URGBC/H-PT specification, 'Version A2 date 2026/01/23' ↗ day