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Nationstar TBA-C1010 IC (16-bit, unnamed)

1-wire RGB · Nationstar · nationstar

Channels
RGB
Bits / channel
16
Supply
4.2–5.5 V
PWM
4 kHz
Backup data
no
Packages
1

A 16-bit, low-current driver-and-LED in a 1.0 x 1.0 mm package. The sheet calls it a “three-channel 16 bit PWM constant-current output lamp-and-driver in one” product and names no IC (the AB1002A of the sibling TBA-T2020M sheet is not mentioned here).

Datasheets disagree: the overview (page 3) puts the quiescent current at 760 uA while the IC table (page 7) says 270 typical to 360 maximum uA; the IC table’s low-level output voltage reads “VCC+0.1” (a typo for GND+0.1 in the sibling sheets); the frame-rate paragraph (page 8) says the chip supports two channel bit widths and two working modes, with a “dual backup frame” mode at double frame rate, but the pin table has a single DI and a single DO and the feature list mentions only 16 bits. Nothing in the pin table supports a second data path. For scale: the output current is 2.3 mA per colour (8 mA absolute maximum) and the typical luminous intensities are R 10, G 34, B 7 mcd at that current.

Refresh & flicker

16-bit (65536 level) PWM at 4 kHz (page 3), 3.8 / 4 / 4.2 kHz in the electrical table (page 7). Supply 4.2-5.5 V with built-in over-voltage protection; 3.3 V data levels supported; up to 1000 cascaded pixels; data rate 800 kbps. Quiescent current 270 / 360 uA (table) - the overview on page 3 says 760 uA. Output current: 2.3 mA per colour (table), absolute maximum 8 mA; input thresholds 0.7 / 0.3 x VCC; power under 300 mW; ESD 2 kV.

Timing

Nationstar TBA-C1010 IC (16-bit, unnamed) bit timingNationstar TBA-C1010 IC (16-bit, unnamed) bit timing: a zero bit is 320 nanoseconds high then 960 low; a one bit is 960 high then 320 low; reset 80 microseconds low1 · Bit encoding, to scaleDINhighlowbit 0 period 1280 nsbit 1 period 1280 nsT0H 320 nsT1H 960 nsT0L 960 nsT1L 320 ns"0" bit"1" bit02505007501000125015001750200022502500time, ns2 · One frame: 48 bits, most-significant bit firstDIN115011001010110010001510011010100110101150010110100101100bitch 1 · 16 bitsch 2 · 16 bitsch 3 · 16 bitsChannel order not recorded for this protocol · frame = 48 × ~1280 ns ≈ 61.4 µs · example data, first bits 1 0 1 …3 · RESET / latchlast bits of frame 1first bits of frame 2LEDs latch the data they receivedRESET: DIN low ≥ 80 µs (not to scale)4 · Cascade: each DOUT feeds the next DINMCULED 1DINDOUTLED 2DINDOUTLED NDINDOUTLED 1 keeps the first 48 bits, re-shapes the signal and sends the rest out on DOUT;LED 2 keeps the next 48, and so on. The last LED's DOUT is left unconnected.
T0H 320 / T0L 960 · T1H 960 / T1L 320 ns · period 1280 ns · reset 80 µs source: datasheet
SourceT0HT0LT1HT1LPeriodRateReset±
datasheet ↗ 320 ns 960 ns 960 ns 320 ns 1280 ns 781 kHz 80 µs —
Code 0 is 320 ns high then 960 ns low, Code 1 is 960 ns high then 320 ns low, frame sync is a low idle of more than 80 us (all as drawn on page 8). The stated code rate is 800 kbps (1.25 us per bit), which does not equal the 1.28 us the drawn times add up to. The chip receives 48 bits per pixel, R, G and B as 16-bit words in that order (R1 G1 B1 … Rn Gn Bn as drawn); the frame diagram shows all of the red, green and blue words of one pixel in a row.

Library support

Not checked. 16-bit data words, so not a drop-in for 8-bit libraries.

Parts using this protocol

Dating evidence

Evidence, not a release date. A library commit proves the part existed by that date and says nothing about how long before.

  • 2022-12-02 datasheet revision Nationstar TBA-C1010MB-J2I16 specification, release date (发放日期) on the cover; version A ↗ day