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TX1818

1-wire RGB · TCWIN · tx18xx

Channels
RGB
Bits / channel
8
Supply
10.8–13.2 V
PWM
8 kHz
Backup data
yes
Packages
4

The 12 V member of the TX18xx numbering: it keeps the 5050 / 3535 packages of the 5 V TX1812 / TX1813 parts, changes the data order to RGB and the supply to 10.8-13.2 V, and fixes the output at 9 mA per channel. Four-pad 5050 (CXJ), six-pad 5050 (BJJ), and two 3535 six-pad pinouts (G with a backup data input, H without). The backup input is present on the G/B pinouts and absent (NC) on the C and H ones, so it is optional rather than universal; the sheets never explain it. TCWIN’s T74 and T75 are other 12 V parts with similar timing but a 9-14 V range, 8.5 mA drive and a 200 us reset.

No claim is made that the timing equals any other maker’s 12 V chip (WS2815 and SK6812HV print different numbers).

Refresh & flicker

12 V supply (10.8-13.2 V, 12 V typical, absolute maximum -0.4 to 14 V); 9 mA per channel; data order R, G, B (red first), 24 bits per pixel; 8 kHz PWM, 2 mA static, 800 kHz data rate, delay at most 200 ns, input thresholds 4 V high / 1 V low at VDD = 12 V, 2 kV ESD.

Timing

TX1818 bit timingTX1818 bit timing: a zero bit is 300 nanoseconds high then 900 low; a one bit is 900 high then 300 low; tolerance plus or minus 50 nanoseconds; reset 80 microseconds low1 · Bit encoding, to scaleDINhighlowbit 0 period 1200 nsbit 1 period 1200 nsT0H 300 ±50 nsT1H 900 ±50 nsT0L 900 ±50 nsT1L 300 ±50 ns"0" bit"1" bit020040060080010001200140016001800200022002400time, ns± tolerance on each falling edge2 · One frame: 24 bits, most-significant bit firstDIN170110010007100110101700101100bitch 1 · 8 bitsch 2 · 8 bitsch 3 · 8 bitsChannel order not recorded for this protocol · frame = 24 × ~1200 ns ≈ 28.8 µs · example data, first bits 1 0 1 …3 · RESET / latchlast bits of frame 1first bits of frame 2LEDs latch the data they receivedRESET: DIN low ≥ 80 µs (not to scale)4 · Cascade: each DOUT feeds the next DINMCULED 1DINDOUTLED 2DINDOUTLED NDINDOUTLED 1 keeps the first 24 bits, re-shapes the signal and sends the rest out on DOUT;LED 2 keeps the next 24, and so on. The last LED's DOUT is left unconnected.BIN (backup): tied to the previous pixel's DIN
T0H 300 / T0L 900 · T1H 900 / T1L 300 ns · ±50 ns · period 1200 ns · reset 80 µs source: datasheet
SourceT0HT0LT1HT1LPeriodRateReset±
datasheet ↗ 300 ns 900 ns 900 ns 300 ns 1200 ns 833 kHz 80 µs 50 ns
Typical values with a symmetric ±0.05 us tolerance: T0H 0.3 us, T0L 0.9 us, T1H 0.9 us, T1L 0.3 us, reset at least 80 us (the HLJ and HXJ sheets print “80 us” and “>0 us”).

Library support

Not checked against FastLED’s chipset list or the other libraries’ source.

Parts using this protocol

Dating evidence

Evidence, not a release date. A library commit proves the part existed by that date and says nothing about how long before.

  • 2023-03-27 datasheet revision TCWIN TX1818 specification covers (CXJ / BJJ / GLJ / HLJ / HXJ): date 20230327, version A2 ↗ day