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Xinglight 2812B-T 3535 (4.0-5.5 V, 12 mA, slow-bit timing)

1-wire RGB · Xinglight · xinglight

Channels
RGB
Bits / channel
8
Supply
4–5.5 V
PWM
—
Backup data
no
Packages
1

No datasheet names the driver IC or its maker: the sheets are Xinglight letterhead documents titled with the SKU only, so this protocol is defined by the figures the sheets print (supply, per-channel current, timing table, pin set), not by a known die.

Datasheets disagree within the one sheet: the p7 table prints reset 100 us min / 150 us typ and note b says the minimum reset is 100 us (gaps over 35 us may be read as RESET); the p8 “Recommended value of controller timing” table prints T0H 0.28, T1H 0.9 (table typ 0.85), T0L > 1.72, T1L > 1.1, cycle > 2.0 us and “reset > 30 us, recommended 80 us”. The optical table is measured at IF = 20 mA though the output current is 12 mA.

Refresh & flicker

FOSC 800 kHz and 10 MHz, transmission delay 160 ns typ (300 max), VIH 0.7 VDD, VIL 0.3 VDD, hysteresis 0.35 V, power 250 mW, data rate 800 kbps (3535-T sheet C22461794).

Timing

Xinglight 2812B-T 3535 (4.0-5.5 V, 12 mA, slow-bit timing) bit timingXinglight 2812B-T 3535 (4.0-5.5 V, 12 mA, slow-bit timing) bit timing: a zero bit is 280 nanoseconds high then 1720 low; a one bit is 850 high then 1100 low; reset 150 microseconds low1 · Bit encoding, to scaleDINhighlowbit 0 period 2000 nsbit 1 period 1950 nsT0H 280 nsT1H 850 nsT0L 1720 nsT1L 1100 ns"0" bit"1" bit0500100015002000250030003500time, nsDatasheet lists unequal bit periods (2000 vs 1950 ns); each bit is drawn with its own.2 · One frame: 24 bits, most-significant bit firstDIN170110010007100110101700101100bitch 1 · 8 bitsch 2 · 8 bitsch 3 · 8 bitsChannel order not recorded for this protocol · frame = 24 × ~2000 ns ≈ 48 µs · example data, first bits 1 0 1 …3 · RESET / latchlast bits of frame 1first bits of frame 2LEDs latch the data they receivedRESET: DIN low ≥ 150 µs (not to scale)4 · Cascade: each DOUT feeds the next DINMCULED 1DINDOUTLED 2DINDOUTLED NDINDOUTLED 1 keeps the first 24 bits, re-shapes the signal and sends the rest out on DOUT;LED 2 keeps the next 24, and so on. The last LED's DOUT is left unconnected.
T0H 280 / T0L 1720 · T1H 850 / T1L 1100 ns · reset 150 µs source: datasheet
SourceT0HT0LT1HT1LPeriodRateReset±
datasheet ↗ 280 ns 1720 ns 850 ns 1100 ns 2000 ns 500 kHz 150 µs —
Min/typ/max: Tin0h 0.20/0.28/0.35 us, Tin1h 0.62/0.85/1.0 us, T0L 1.55/1.72/30 us, T1L 1.1/1.1/30 us, cycle 1.75 us min, 35 us max, reset 100 us min, 150 us typ. The values recorded are the typicals, so t0h + t0l = 2.0 us and t1h + t1l = 1.95 us: the bit period is left null because the table prints no typical cycle.

Clones & compatibility

“Compatible” is never stated bare here — each relationship carries how strong the claim is, and what bites if you assume too much.

  • protocol compatible WS2812B

    Only the title says WS2812B-T. Its low times (T0L at least 1.55 us, T1L at least 1.1 us) make a bit at least 1.75 us long, over twice the WS2812B 1.25 us; a controller sending WS2812B-speed bits does not meet the table. source ↗

Library support

Not checked against any library. The sheets state a 24-bit (32-bit for IC-01W) frame sent high bit first at 800 kbps.

Parts using this protocol

Dating evidence

Evidence, not a release date. A library commit proves the part existed by that date and says nothing about how long before.

  • 2025-09-08 estimate PDF CreationDate metadata of Xinglight sheet XL-3535RGBC-2812B-T (LCSC C22461794); the sheet has no revision table, so this is only the date the PDF file was produced ↗ day