addressable.wiki

Xinglight SK6812B with BIN input (3.5-7.5 V, 12 mA)

1-wire RGB · Xinglight · xinglight

Channels
RGB
Bits / channel
8
Supply
3.5–7.5 V
PWM
4 kHz
Backup data
yes
Packages
1

No datasheet names the driver IC or its maker: the sheets are Xinglight letterhead documents titled with the SKU only, so this protocol is defined by the figures the sheets print (supply, per-channel current, timing table, pin set), not by a known die.

Backup input: p2 says “In addition to DIN, the chip is additionally designed with an FDIN input terminal to receive the DIN data of the previous chip, that is, the DOUT data of the previous chip”; the pin table calls pin 4 BIN, “auxiliary signal input”. The sheet’s own two phrasings differ (DIN of the previous chip, or DOUT of the previous chip) and wiring was not tested.

Datasheets disagree: p2 says the output PWM “signal cycle is 4 ms” while the electrical table gives FPWM 4 kHz; the title says SK6812B but the timing table (0.295/0.595/0.595/0.295 us) is not the OPSCO SK6812 sheet’s 0.3/0.9/0.6/0.6.

Refresh & flicker

FPWM 4 kHz and FOSC 800 kHz (max 1100 kHz); prose says the PWM “signal cycle is 4 ms” (about 250 Hz).

Timing

Xinglight SK6812B with BIN input (3.5-7.5 V, 12 mA) bit timingXinglight SK6812B with BIN input (3.5-7.5 V, 12 mA) bit timing: a zero bit is 295 nanoseconds high then 595 low; a one bit is 595 high then 295 low; reset 80 microseconds low1 · Bit encoding, to scaleDINhighlowbit 0 period 890 nsbit 1 period 890 nsT0H 295 nsT1H 595 nsT0L 595 nsT1L 295 ns"0" bit"1" bit02004006008001000120014001600time, ns2 · One frame: 24 bits, most-significant bit firstDIN170110010007100110101700101100bitch 1 · 8 bitsch 2 · 8 bitsch 3 · 8 bitsChannel order not recorded for this protocol · frame = 24 × ~890 ns ≈ 21.4 µs · example data, first bits 1 0 1 …3 · RESET / latchlast bits of frame 1first bits of frame 2LEDs latch the data they receivedRESET: DIN low ≥ 80 µs (not to scale)4 · Cascade: each DOUT feeds the next DINMCULED 1DINDOUTLED 2DINDOUTLED NDINDOUTLED 1 keeps the first 24 bits, re-shapes the signal and sends the rest out on DOUT;LED 2 keeps the next 24, and so on. The last LED's DOUT is left unconnected.BIN (backup): tied to the previous pixel's DIN
T0H 295 / T0L 595 · T1H 595 / T1L 295 ns · period 890 ns · reset 80 µs source: datasheet
SourceT0HT0LT1HT1LPeriodRateReset±
datasheet ↗ 295 ns 595 ns 595 ns 295 ns 890 ns 1124 kHz 80 µs —
Typical column only: 0.295/0.595/0.595/0.295 us, cycle min 0.89 us, reset min 80 us.

Clones & compatibility

“Compatible” is never stated bare here — each relationship carries how strong the claim is, and what bites if you assume too much.

  • protocol compatible SK6812

    Only the title (XL-3527RGBC-SK6812B, "XL-3527 (6812)" in the description) says SK6812; the sheet adds an auxiliary input BIN that the sheet describes as receiving the DIN data of the previous chip (i.e. the DOUT of the chip two positions upstream) so that one dead pixel does not stop the chain. The OPSCO SK6812 has no such pin. source ↗

Library support

Not checked against any library. The sheets state a 24-bit (32-bit for IC-01W) frame sent high bit first at 800 kbps.

Parts using this protocol

Dating evidence

Evidence, not a release date. A library commit proves the part existed by that date and says nothing about how long before.

  • 2025-09-08 estimate PDF CreationDate metadata of Xinglight sheet XL-3527RGBC-SK6812B (LCSC C51900946); the sheet has no revision table, so this is only the date the PDF file was produced ↗ day