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Xinglight SK6812B with FDIN input (5 mA, 0.25/0.47 us windows)

1-wire RGB · Xinglight · xinglight

Channels
RGB
Bits / channel
8
Supply
3.5–5.5 V
PWM
1.5 kHz
Backup data
yes
Packages
1

No datasheet names the driver IC or its maker: the sheets are Xinglight letterhead documents titled with the SKU only, so this protocol is defined by the figures the sheets print (supply, per-channel current, timing table, pin set), not by a known die.

The sheet has the SK6812B prose (p2) with the FDIN input and a 6-pin table (1 DO, 2 NC, 3 GND, 4 DI2, 5 DI1, 6 VDD); it never says which of DI1/DI2 is FDIN, so both are recorded as data inputs.

Datasheets disagree: title and prose say SK6812B, the timing table is the 0.25/0.47 us set printed on the Xinglight 2812B 1515/2020/3528 sheets (reset 80 us); p2 says the PWM “signal cycle is 4 ms” against fPWM 1.5 kHz in the table.

Refresh & flicker

fPWM 1.5 kHz, fDATA 800 kHz, operating current 0.5 mA, propagation delay 0.21 us typ; prose says the PWM “signal cycle is 4 ms”.

Timing

Xinglight SK6812B with FDIN input (5 mA, 0.25/0.47 us windows) bit timingXinglight SK6812B with FDIN input (5 mA, 0.25/0.47 us windows) bit timing: a zero bit is 250 nanoseconds high then 1000 low; a one bit is 850 high then 400 low; reset 80 microseconds low1 · Bit encoding, to scaleDINhighlowbit 0 period 1250 nsbit 1 period 1250 nsT0H 250 nsT1H 850 nsT0L 1000 nsT1L 400 ns"0" bit"1" bit02505007501000125015001750200022502500time, ns2 · One frame: 24 bits, most-significant bit firstDIN170110010007100110101700101100bitch 1 · 8 bitsch 2 · 8 bitsch 3 · 8 bitsChannel order not recorded for this protocol · frame = 24 × ~1250 ns ≈ 30 µs · example data, first bits 1 0 1 …3 · RESET / latchlast bits of frame 1first bits of frame 2LEDs latch the data they receivedRESET: DIN low ≥ 80 µs (not to scale)4 · Cascade: each DOUT feeds the next DINMCULED 1DINDOUTLED 2DINDOUTLED NDINDOUTLED 1 keeps the first 24 bits, re-shapes the signal and sends the rest out on DOUT;LED 2 keeps the next 24, and so on. The last LED's DOUT is left unconnected.BIN (backup): tied to the previous pixel's DIN
T0H 250 / T0L 1000 · T1H 850 / T1L 400 ns · period 1250 ns · reset 80 µs source: datasheet
SourceT0HT0LT1HT1LPeriodRateReset±
datasheet ↗ 250 ns 1000 ns 850 ns 400 ns 1250 ns 800 kHz 80 µs —
Min/typ/max table: Tin0h typ 0.25 us max 0.47 us (no min), Tin1h 0.58/0.85/1.0 us, T0L typ 1.0 us, T1L typ 0.4 us, cycle min 1.2 us typ 1.25 us, reset min 80 us. Note: “0” code high time must be under 0.47 us, “1” code high time over 0.58 us. The values recorded are the typical column; T0H/T1L are not midpoints.

Clones & compatibility

“Compatible” is never stated bare here — each relationship carries how strong the claim is, and what bites if you assume too much.

  • protocol compatible SK6812

    Only the title (XL-2020RGBC-SK6812B) says SK6812. The sheet adds a second data input (FDIN, pins DI1/DI2) and 5 mA drive; its timing table is the same 0.25/0.47 us set as the Xinglight 1515/2020 "2812B" sheets, which has nothing in common with the OPSCO SK6812 sheet. source ↗

Library support

Not checked against any library. The sheets state a 24-bit (32-bit for IC-01W) frame sent high bit first at 800 kbps.

Parts using this protocol

Dating evidence

Evidence, not a release date. A library commit proves the part existed by that date and says nothing about how long before.

  • 2025-09-08 estimate PDF CreationDate metadata of Xinglight sheet XL-2020RGBC-SK6812B (LCSC C5349956); the sheet has no revision table, so this is only the date the PDF file was produced ↗ day