2.2 × 2.2 mm 6 pins top-emitting

TX1816Z

2020 · smd · TX1816 · TCWIN

1-wire RGB 4–5.5 V backup data line active

At a glance

Colour
RGB16 bits per channel
Data
1-wiretimed pulses on one line
Supply
4–5.5 Vbackup data line
Size
2.2 × 2.2 × 1.1 mm6 pins · top
Max current
—per-channel not recorded
PWM
4 kHzreset 80 µs
Library support
FastLED WLED Adafruit

TCWIN’s 16-bit-per-channel LED driver in a 2.2 x 2.2 x 1.05 mm six-pad package (LCSC: SMD2020-6P). Sheet version A1, cover date 2021-11-15, the oldest TCWIN sheet in the set. Pins (p5): 1 DO, 2 NC (the PCB must connect it to pin 5 DIN), 3 GND, 4 FDIN (backup data input), 5 DIN, 6 VDD (+5 V). Numbered counter-clockwise from the polarity-marked bottom-right corner. The suggested land pattern joins pads 2 and 5 with one bar.

The sheet is the only TCWIN text that explains the backup port: “a backup communication port, so that when one chip in the cascade is damaged the following ones are not affected”. It describes a 3-channel high-grey constant-current driver with gamma correction, a 48-bit data frame (G15…G0 R15…R0 B15…B0, high bit first, GRB order), a separate 15-bit gain word (five bits per channel, default 08H = 3.63 mA, table 0.71-12.00 mA), 1.3 MHz data rate and 4 kHz PWM.

Datasheets disagree with themselves: the feature list says the default constant-current output is 3.5 mA while the gain table (p9) says default setting 08H gives 3.63 mA; the absolute-maximum table gives VDD 3.0-5.5 V while the electrical table gives 4 / 5 / 5.5 V; the sheet never says how the 15-bit gain word is sent relative to the 48-bit frame. LCSC lists TX1816ZWBN-F01 as a 5-pin 2.2 x 2.2 mm part while the only TX1816 sheet is six-pin. The cover says 2.2 x 2.2 x 1.05 mm while the LCSC package name is “2020”.

Variants

One row per orderable SKU. Everything not listed is inherited from the part above.

Order codeFaceLensWhite PinsSiliconStatusFirst seenDatasheet
TX1816ZLN-F01 — — — 6 — active 2021-11-15 A1
Output 0.71-12 mA per channel by gain setting, default 3.63 mA. LCSC stock 3,290 when checked. LCSC stock 3,290 on 2026-10-15.
TX1816ZWBN-F01 — — — — — active 2021-11-15 A1
No datasheet is listed on LCSC for this SKU. Package, pin order and drawing are taken from the sibling sheet TX1816ZLN-F01 because both share IC code 1816 and package letter Z; that is an inference from the part number, not something any sheet states. Drive current, timing window and the meaning of the remaining letters are not confirmed for this SKU. LCSC lists this SKU as a 5-pin 2.2 x 2.2 mm package while the sheet for TX1816ZLN-F01 is six-pin, so the pinout is NOT inherited. Stock 0 when checked. LCSC stock 0 on 2026-10-15.

Pinout

TX1816ZLN-F01
TX1816Z 2020 package, top and side viewPin 1 is ringed. pin 1 DO (data out), pin 2 NC (no connect), pin 3 GND (ground), pin 4 FDIN (backup in), pin 5 DIN (data in), pin 6 VDD (power).11 DOdata out22 NCno connect33 GNDground44 FDINbackup in55 DINdata in66 VDDpower2.2 mm2.2 mmtop view1.1 mmside view
  • Data
  • No connect
  • Ground
  • Backup data
  • Power
  • Pin 1
  • Cut corner

Outline and pin positions checked against the manufacturer datasheet (C7495090 TX1816ZLN-F01 rev A1 p4). Pin 1 (DO) at the polarity-marked corner, bottom-right. Pads 0.5 x 0.32 mm with 0.28 mm gaps. What this means.

  1. 1 DO data out
  2. 2 NC nc
  3. 3 GND ground
  4. 4 FDIN backup data in
  5. 5 DIN data in
  6. 6 VDD power

Protocol — TX1816

Timings shown from datasheet.

TX1816 bit timingTX1816 bit timing: a zero bit is 240 nanoseconds high then 480 low; a one bit is 480 high then 240 low; reset 80 microseconds low1 · Bit encoding, to scaleDINhighlowbit 0 period 720 nsbit 1 period 720 nsT0H 240 nsT1H 480 nsT0L 480 nsT1L 240 ns"0" bit"1" bit0200400600800100012001400time, ns2 · One frame: 48 bits, most-significant bit firstDIN115011001010110010001510011010100110101150010110100101100bitch 1 · 16 bitsch 2 · 16 bitsch 3 · 16 bitsChannel order not recorded for this protocol · frame = 48 × ~720 ns ≈ 34.6 µs · example data, first bits 1 0 1 …3 · RESET / latchlast bits of frame 1first bits of frame 2LEDs latch the data they receivedRESET: DIN low ≥ 80 µs (not to scale)4 · Cascade: each DOUT feeds the next DINMCULED 1DINDOUTLED 2DINDOUTLED NDINDOUTLED 1 keeps the first 48 bits, re-shapes the signal and sends the rest out on DOUT;LED 2 keeps the next 48, and so on. The last LED's DOUT is left unconnected.BIN (backup): tied to the previous pixel's DIN
T0H 240 / T0L 480 · T1H 480 / T1L 240 ns · period 720 ns · reset 80 µs source: datasheet

Dating evidence

Nobody announces these parts, so this records what we can actually cite rather than a release date. Library support proves only that the part existed by that date.

  • 2021-11-15 datasheet revision TCWIN TX1816ZLN-F01 specification cover: date 20211115, version A1 ↗ day

Where to buy

Stub data — a few rows so purchase links can grow later. Prices are not tracked.

Similar parts

Same protocol or package first, then the same data scheme and colour channels.

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