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TX1816

1-wire RGB · TCWIN · tx18xx

Channels
RGB
Bits / channel
16
Supply
4–5.5 V
PWM
4 kHz
Backup data
yes
Packages
1

TCWIN’s 16-bit-per-channel IC, described as a “three-channel high-grey LED constant-current driver” with MCU single-wire interface, data latch, constant-current drive, PWM and gamma correction. Dual input/output for a backup communication port: “so that when one chip in the cascade is damaged the following ones are not affected” (sheet section 1). It forwards after receiving 48 bits, holds DO low until then, and latches the new frame on an 80 us low reset. Output current per channel is 0.71-12 mA by a 5-bit gain; default gain 08H is 3.63 mA. Static current 0.8 mA, 3000 V HBM, junction -40 to 85 C. The sheet recommends a resistor from DO to the next DIN and a capacitor between VDD and GND (printed “104uf”; 104 is the usual code for 0.1 uF).

Datasheets disagree with themselves: the feature list says the default constant-current output is 3.5 mA but the gain table says the default setting 08H is 3.63 mA; the absolute-maximum supply is 3.0-5.5 V but the electrical table gives VDD 4 / 5 / 5.5 V (recorded range 4.0-5.5 V); the sheet does not say how the 15 gain bits are framed relative to the 48 data bits.

No other TX1816 sheet exists on LCSC. Not a 24-bit protocol; no compatibility with a 24-bit chip is claimed.

Refresh & flicker

48-bit frame per pixel (G15…G0, R15…R0, B15…B0, high bit first), 1.3 MHz data rate (1 MHz minimum), 4 kHz PWM, 65536 grey levels, gamma correction. A separate 15-bit gain word (five bits per channel) sets 0.71-12.00 mA; the sheet says nothing about when it is sent.

Timing

TX1816 bit timingTX1816 bit timing: a zero bit is 240 nanoseconds high then 480 low; a one bit is 480 high then 240 low; reset 80 microseconds low1 · Bit encoding, to scaleDINhighlowbit 0 period 720 nsbit 1 period 720 nsT0H 240 nsT1H 480 nsT0L 480 nsT1L 240 ns"0" bit"1" bit0200400600800100012001400time, ns2 · One frame: 48 bits, most-significant bit firstDIN115011001010110010001510011010100110101150010110100101100bitch 1 · 16 bitsch 2 · 16 bitsch 3 · 16 bitsChannel order not recorded for this protocol · frame = 48 × ~720 ns ≈ 34.6 µs · example data, first bits 1 0 1 …3 · RESET / latchlast bits of frame 1first bits of frame 2LEDs latch the data they receivedRESET: DIN low ≥ 80 µs (not to scale)4 · Cascade: each DOUT feeds the next DINMCULED 1DINDOUTLED 2DINDOUTLED NDINDOUTLED 1 keeps the first 48 bits, re-shapes the signal and sends the rest out on DOUT;LED 2 keeps the next 48, and so on. The last LED's DOUT is left unconnected.BIN (backup): tied to the previous pixel's DIN
T0H 240 / T0L 480 · T1H 480 / T1L 240 ns · period 720 ns · reset 80 µs source: datasheet
SourceT0HT0LT1HT1LPeriodRateReset±
datasheet ↗ 240 ns 480 ns 480 ns 240 ns 720 ns 1389 kHz 80 µs —
Min/typ/max at VDD = 5 V: T0H 200/240/280 ns, T0L 400/480/560 ns, T1H 400/480/560 ns, T1L 200/240/280 ns, reset at least 80 us. Bit period 720 ns, about 1.39 MHz, in line with the 1.3 MHz typical rate.

Library support

Not checked against FastLED’s chipset list or the other libraries’ source.

Parts using this protocol

Dating evidence

Evidence, not a release date. A library commit proves the part existed by that date and says nothing about how long before.

  • 2021-11-15 datasheet revision TCWIN TX1816ZLN-F01 specification cover: date 20211115, version A1 ↗ day