AB1002A (Nationstar dual-input)
1-wire RGB · Nationstar · nationstar
- Channels
- RGB
- Bits / channel
- —
- Supply
- 3.3–12 V
- PWM
- —
- Backup data
- no
- Packages
- 1
The only IC the sheet names is AB1002A, in the timing section: “AB1002A uses a patent-licensed enhanced adaptive duty-cycle code protocol”. The overview calls the product a full-colour SMD component with “white material, two-channel transmission, and 8-bit or 16-bit transmit data”.
WHAT THE SHEET SAYS ABOUT THE TWO INPUTS (and nothing more): the pin table lists two data inputs, DI0 (pin 5) and DI1 (pin 4), and two data outputs, DO0 (pin 3) and DO1 (pin 2). Page 6 gives three bench tests at 1 Mbps, 4 frames of 144 bits, 80 us idle: (1) DI0 sends all zeros with DI1 tied to GND - the RGB LEDs must stay off and DO0 and DO1 must both show data; (2) DI0 sends all ones with DI1 floating
- the RGB LEDs must be fully on; (3) DI1 sends all ones with DI0 floating - the RGB LEDs must be fully on (“分光”, the light-splitting/binning measurement, is also noted). Whether the two inputs carry independent or redundant data, what DO0/DO1 each output, and what the 8-bit and 16-bit modes are selected by are not explained. It is therefore NOT modelled as a backup line.
The pages carry a “temporary version” (临时版) watermark, so this is a pre-release sheet. The cover and the protocol page differ in how they count the data: the overview says 8-bit or 16-bit transmit data, the protocol page says 24 or 48 bits per pixel (8 or 16 per colour) - the same thing; the catalogue leaves bits per channel null because both widths are claimed. Not verified on hardware.
Refresh & flicker
IC table (printed page 5): VCC 3.3 to 12 V (5 V typical), working current 0.8 mA maximum at 1.6 MHz data, idle 0.7 mA, data rate 400 kHz to 1.6 MHz adaptive, input thresholds 0.7 / 0.3 x VCC, output VCC-0.3 / GND+0.1, per-colour LED current 5 to 15 mA (R and G 9-15 mA, B 5-9 mA), die-to-die current mismatch 1 to 3 percent. Absolute maximum: IOUT 40 mA, power under 300 mW, ESD 4 kV HBM. No PWM frequency is printed.
Timing
| Source | T0H | T0L | T1H | T1L | Period | Rate | Reset | ± |
|---|---|---|---|---|---|---|---|---|
| datasheet ↗ | 250 ns | 750 ns | 750 ns | 250 ns | 1000 ns | 1000 kHz | 80 µs | — |
| The sheet defines the code by DUTY CYCLE, not by fixed times: Code 0 is 1/4 T high then 3/4 T low, Code 1 is 3/4 T high then 1/4 T low, decided at the T/2 point (high longer than T/2 is a 1, shorter is a 0), and the chip supports any data rate from 400 kbps to 1.6 Mbps (“adaptive”; the forwarded rate follows the controller’s). The figures here are the sheet’s own test set-up at 1 Mbps with a 1:3 duty: 1 code = 750 ns high / 250 ns low, 0 code = 250 ns high / 750 ns low. Frame sync is a low (idle) period of more than 80 us (“帧同步讯号为低电平 Idle >80us”; the test sends frames of 144 bits with an 80 us gap). The sheet says the chip receives 24 or 48 bits per pixel, i.e. 8 or 16 bits per colour; the colour order is not printed. | ||||||||
Library support
Not checked. The adaptive duty-cycle code is not a fixed-timing protocol, so a stream built for a fixed-timing part is not assumed to work.
Parts using this protocol
Dating evidence
Evidence, not a release date. A library commit proves the part existed by that date and says nothing about how long before.
- 2022-07-20 datasheet revision Nationstar TBA-T2020M-J1I16 specification, release date (发放日期) on the cover; version A; the pages carry a 'temporary version' (临时版) watermark ↗ day