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TCWIN T65 group

1-wire RGB · TCWIN · tx18xx

Channels
RGB
Bits / channel
8
Supply
3–5.5 V
PWM
4 kHz
Backup data
no
Packages
2

TCWIN T-code sheets (headed “RGB LED (built-in IC)”, “Type Txx”) give no IC name or “naming principle” beyond the code itself. This protocol is the group of T-codes whose printed tables are identical; the sheets do not say the parts share one die. The first-issue (A0) sheets: operating temperature -30 to 70 C, supply 3.0-5.5 V, ESD 5.5 kV, input thresholds printed as typicals only (0.5 VDD / 0.3 VDD), and a logic-input absolute maximum printed as -0.5 to 0.5 V, which looks like a typo for 5.5 V.

Refresh & flicker

Data rate 800 kHz typical, 4 kHz PWM, 24-bit GRB, 12 mA per channel (typical only), 0.5 mA static, delay 0.07 us, rise/fall 0.33 us.

Timing

TCWIN T65 group bit timingTCWIN T65 group bit timing: a zero bit is 300 nanoseconds high then 900 low; a one bit is 800 high then 900 low; reset 80 microseconds low1 · Bit encoding, to scaleDINhighlowbit 0 period 1200 nsbit 1 period 1700 nsT0H 300 nsT1H 800 nsT0L 900 nsT1L 900 ns"0" bit"1" bit025050075010001250150017502000225025002750time, nsDatasheet lists unequal bit periods (1200 vs 1700 ns); each bit is drawn with its own.2 · One frame: 24 bits, most-significant bit firstDIN170110010007100110101700101100bitch 1 · 8 bitsch 2 · 8 bitsch 3 · 8 bitsChannel order not recorded for this protocol · frame = 24 × ~1700 ns ≈ 40.8 µs · example data, first bits 1 0 1 …3 · RESET / latchlast bits of frame 1first bits of frame 2LEDs latch the data they receivedRESET: DIN low ≥ 80 µs (not to scale)4 · Cascade: each DOUT feeds the next DINMCULED 1DINDOUTLED 2DINDOUTLED NDINDOUTLED 1 keeps the first 24 bits, re-shapes the signal and sends the rest out on DOUT;LED 2 keeps the next 24, and so on. The last LED's DOUT is left unconnected.
T0H 300 / T0L 900 · T1H 800 / T1L 900 ns · reset 80 µs source: datasheet
SourceT0HT0LT1HT1LPeriodRateReset±
datasheet ↗ 300 ns 900 ns 800 ns 900 ns 1200 ns 833 kHz 80 µs —
Min/typ/max as printed: T0H 200/300/400 ns, T0L 600/900/- ns, T1H 600/800/900 ns, T1L 600/900/- ns, reset at least 80 us. The printed T1L (600 ns minimum, 900 typical) is as long as T0L, which would make a one code a long pulse with a long low; it is almost certainly a sheet error (a one code should have a short low) and is recorded as printed.

Library support

Not checked against FastLED’s chipset list or the other libraries’ source.

Parts using this protocol

Dating evidence

Evidence, not a release date. A library commit proves the part existed by that date and says nothing about how long before.

  • 2024-07-27 datasheet revision TCWIN T65 and T77 specification covers: date 20240727, version A0 ↗ day