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TONYU 9822

SPI RGB · TONYU · tonyu

Channels
RGB
Bits / channel
—
Supply
4.5–5.5 V
PWM
4.6 kHz
Backup data
no
Packages
1

TONYU’s two-wire (data plus clock) IC in a six-pad 5050 package. The “9822” in the part number is not explained by the sheet.

Datasheets disagree with themselves: page 2 says each channel outputs 16-bit (65536-step) linear-current gray scale, but the page-8 data frame is 8 bits per colour (256 levels, a table of 0/256 to 255/256 duty) plus a 5-bit (32 step) brightness field. The frame diagram is the more detailed of the two and is what the catalogue assumes; bits per channel is therefore left null. The page-4 maximum supply voltage reads “5…3” (a typo for 5.3 V).

Refresh & flicker

PWM 4.6 kHz in the IC table (page 4); the product description on page 2 says a refresh rate “up to 4 KHz”, and the switching table (page 7) gives a 4.15 kHz LED scan frequency. Quiescent 1 mA, chip internal supply 5.0 V typical (5.3 maximum). Default output 18 mA per channel with REXT floating (adjustable with an external resistor), 20 mA maximum LED output current.

Frame format

TONYU 9822 SPI frameTONYU 9822 clocked frame: start frame, one 32-bit LED frame per pixel with brightness and colour bytes, and an end frame, plus data and clock waveforms1 · Frame stream (data clocked on CLK)Start frame32 × 0LED 132 bitsLED 232 bits…LED N32 bitsEnd frameclock ≥ N/2 edgeseach LED forwards what it does not keep on DO / CO2 · One LED frame: 32 bits, MSB first111brightch 1 8ch 2 8ch 3 83 marker bits (111), 5-bit global brightness 0–31, then 8-bit channels3 · DATA and CLK, first 8 bits of an LED frameDATACLK11110010111 markerbrightness bits 4..0data changes while CLK is low,LED samples on the rising edgeno fixed bit period: clock rateis set by the host
Frame layout: APA102-family 32-bit LED frames convention, see the protocol notes for end-frame differences
SourceT0HT0LT1HT1LPeriodRateReset±
datasheet ↗ — — — — — — — —
Two-wire clocked interface (SDI/CKI in, SDO/CKO out), so there are no bit-time windows; the clock rate is set by the controller. Printed limits: clock high and low width 17 ns typical each, data set-up time 10 ns maximum (page 4); DIN to DOUT rise and fall 6.8 / 5.5 ns (page 7). The sheet’s frame rate formula is frames per second = 1 / ((64 + 32 x pixels) x CKI period), i.e. 30 frames per second for 1024 pixels at 1 MHz. Data is sampled on the rising edge of CKI, most significant bit first (page 8 diagram). Frame layout from the same page: a 32-bit start frame of zeros, one 32-bit frame per LED (three high bits, a 5-bit brightness field, then Green, Red and Blue bytes), and a 32-bit end frame of ones.

Clones & compatibility

“Compatible” is never stated bare here — each relationship carries how strong the claim is, and what bites if you assume too much.

  • electrically similar SK9822

    Inferred from the part code and the frame diagram only; the TONYU sheet never names OPSCO, SK9822 or APA102. The 32-bit frames (start 32 zero bits, 111 + 5-bit brightness + three colour bytes, end 32 one bits) and the five-bit global brightness are the APA102 / SK9822 layout, with a different colour order (G, R, B here; OPSCO's SK9822 sheets print B, G, R or R, B, G) and a pin order of SDI, CKI, GND, VCC, CKO, SDO that matches OPSCO's SK9822 by position. PWM 4.6 kHz is close to the 4.7 kHz measured on SK9822 by cpldcpu. The 16-bit gray scale in the sheet's text is NOT supported by its own frame diagram (see the notes). source ↗

Library support

Not checked against library source.

Parts using this protocol

Dating evidence

Evidence, not a release date. A library commit proves the part existed by that date and says nothing about how long before.

  • 2019 first documented TONYU DYWH-S505016/RGBC/9822-1T specification, footer 'Copyright 2019, TONYU' (no issue date printed; version A1.0) ↗ year