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TX1812CXA5

1-wire RGB · TCWIN · tx18xx

Channels
RGB
Bits / channel
8
Supply
3.5–5.5 V
PWM
4 kHz
Backup data
no
Packages
0

The same TX1812 part number on a sheet with different timing windows, filed separately because the catalogue keeps timing on the protocol. This is the only 5 mA TX1812 sheet that prints windows this wide; the 0.3 us / 0.9 us typical values coincide with the OPSCO SK6805-EC series typicals (T0H 300, T0L 900, T1H 900, T1L 300 ns) and the T0H window (200-400 ns) equals the SK6805-EC15 sheet’s, but neither sheet claims any relationship.

Whether this is a different die from the rest of TX1812 or the same die described with a different window table is not known. The two sheets carry the same date and version (A2, 2023-03-27).

Refresh & flicker

Same electrical table as the other 5 mA TX1812 sheets: data rate 800 kHz typical, 4 kHz PWM, GRB order.

Timing

TX1812CXA5 bit timingTX1812CXA5 bit timing: a zero bit is 300 nanoseconds high then 900 low; a one bit is 900 high then 300 low; reset 80 microseconds low1 · Bit encoding, to scaleDINhighlowbit 0 period 1200 nsbit 1 period 1200 nsT0H 300 nsT1H 900 nsT0L 900 nsT1L 300 ns"0" bit"1" bit020040060080010001200140016001800200022002400time, ns2 · One frame: 24 bits, most-significant bit firstDIN170110010007100110101700101100bitch 1 · 8 bitsch 2 · 8 bitsch 3 · 8 bitsChannel order not recorded for this protocol · frame = 24 × ~1200 ns ≈ 28.8 µs · example data, first bits 1 0 1 …3 · RESET / latchlast bits of frame 1first bits of frame 2LEDs latch the data they receivedRESET: DIN low ≥ 80 µs (not to scale)4 · Cascade: each DOUT feeds the next DINMCULED 1DINDOUTLED 2DINDOUTLED NDINDOUTLED 1 keeps the first 24 bits, re-shapes the signal and sends the rest out on DOUT;LED 2 keeps the next 24, and so on. The last LED's DOUT is left unconnected.
T0H 300 / T0L 900 · T1H 900 / T1L 300 ns · period 1200 ns · reset 80 µs source: datasheet
SourceT0HT0LT1HT1LPeriodRateReset±
datasheet ↗ 300 ns 900 ns 900 ns 300 ns 1200 ns 833 kHz 80 µs —
Min / “preferred” / max: T0H 200/300/400 ns, T0L 550/900/1200 ns, T1H 550/900/1200 ns, T1L 200/300/400 ns, reset at least 80 us. The middle column is headed “preferred” rather than typical; recorded as the typical. Bit period 1200 ns, which is consistent with the 800 kHz typical data rate printed on the same page (unlike the narrower 245-345 / 545-645 ns windows of the other TX1812 sheets).

Clones & compatibility

“Compatible” is never stated bare here — each relationship carries how strong the claim is, and what bites if you assume too much.

  • protocol compatible TX1812

    Same pin order, supply, 24-bit GRB framing and electrical table; only the printed timing windows differ (T0L/T1H 550-1200 ns here against 545-645 ns). The nominal values of the other TX1812 sheets (295 / 595 ns) lie inside these windows on T0H, T0L, T1H and T1L, so a stream built for those sheets is inside both sets of printed windows; the reverse is not true (900 ns is outside 545-645). Numbers only, never measured. source ↗

Library support

Not checked against FastLED’s chipset list or the other libraries’ source.

Parts using this protocol

No package is catalogued for this protocol yet — it is seeded for family completeness, or it is a driver IC that drives external LEDs rather than shipping as an integrated package.

Dating evidence

Evidence, not a release date. A library commit proves the part existed by that date and says nothing about how long before.

  • 2023-03-27 datasheet revision TCWIN TX1812CXA5-F02 specification cover: date 20230327, version A2 ↗ day