TX1812
1-wire RGB · TCWIN · tx18xx
- Channels
- RGB
- Bits / channel
- 8
- Supply
- 3.5–5.5 V
- PWM
- 4 kHz
- Backup data
- no
- Packages
- 12
TCWIN’s own addressable-LED driver IC family, sold inside TCWIN’s LEDs as TX1812xxxx part numbers. TCWIN (Shenzhen Tiancheng) is not WorldSemi or OPSCO; its sheets print TCWIN’s own letterhead, 5 V supply (3.5-5.5 V), 24-bit GRB single-wire framing with auto-reshaping forwarding, 256 grey levels and 5 or 12 mA per channel depending on the package code. This protocol covers the TX1812 sheets that print the 245/295/345 ns window set; the TX1812CXA5-F02, TX1812CXU-F01 and TX1812CLL sheets print different windows and are separate protocols (tx1812-cxa5, tx1812-cxu, tx1812-rgbw).
Compatibility with other chips is NOT claimed. By the sheets’ own numbers the windows exclude WS2812B’s nominal 400 / 850 ns (T0H 245-345 and T0L 545-645 do not contain them) and SK6812’s 300 / 900 / 600 / 600 ns (T0L 900 is outside 545-645 and T1L 600 is outside 245-345; only T0H and T1H would fit). Whether the silicon tolerates a WS2812B-style stream is untested.
Part-number letters. TCWIN’s sheets label the block after the IC code (e.g. CXA5, DWBA, ZLN) “package size and drive current” and the last group the serial. What the sheets show: the first letter tracks the package (C 5050 4-pin, D 3528, G/H 3535 6-pin, I 2017, L 2528, M 1515, P 1209, Z 2020) and a trailing 5 goes with 5 mA drive (the TX1812Z5 sheet is the only one that says so in words: “2020 built-in 5 mA”). The second letters X, L and W and the other trailing letters (A, B, C, D, N, U) are explained by no sheet; SKUs on LCSC that have no datasheet are therefore filed with their sibling package only as an inference from the part number.
Datasheets disagree with each other: the TX1812CXA5-F02 sheet prints T0H 200/300/400 ns, T0L and T1H 550/900/1200 ns, T1L 200/300/400 ns (see tx1812-cxa5); the TX1812CXU-F01 sheet prints 0.3 / 0.9 / 0.9 / 0.3 us ±0.05 us with a 200 us reset (see tx1812-cxu). The CWCA-F70 sheet also prints an input-high threshold of 0.5 VDD, the LB sheet 0.6 VDD, the others 0.7 VDD.
Refresh & flicker
Data rate 800 kHz typical, 1100 kHz maximum; 3-5 kHz PWM (4 kHz typical), 0.6-1 mA static; the sheets quote at least 1024 pixels at 30 fps. Data order G, R, B, high bit first, 24 bits per pixel; each pixel strips 24 bits and re-shapes and forwards the rest.
Timing
| Source | T0H | T0L | T1H | T1L | Period | Rate | Reset | ± |
|---|---|---|---|---|---|---|---|---|
| datasheet ↗ | 295 ns | 595 ns | 595 ns | 295 ns | 890 ns | 1124 kHz | 80 µs | 50 ns |
| Min/typ/max: T0H 245/295/345 ns, T0L 545/595/645 ns, T1H 545/595/645 ns, T1L 245/295/345 ns, reset at least 80 us; typicals recorded. The sheets also print an 800 kHz typical (1100 kHz maximum) data rate, i.e. a 1250 ns typical bit; the printed windows sum to 790-990 ns, so 800 kHz at the typical rate cannot sit inside them (T0H 345 + T0L 905 is already outside T0L 545-645). The windows fit a rate near 1.1 MHz, which is the printed maximum. Which of the two the silicon really needs has not been measured. | ||||||||
Clones & compatibility
“Compatible” is never stated bare here — each relationship carries how strong the claim is, and what bites if you assume too much.
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protocol compatible of this
TCWIN T62
The T62 electrical and timing tables are word for word the TX1812 5 mA tables (windows, 3.5-5.5 V, 4 kV ESD, 5 mA, GRB). The T62 sheet never mentions TX1812; this edge is based on the identical numbers only.
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protocol compatible of this
TCWIN T63 group
The TX1812 sheets print T0H 245-345 and T0L 545-645 ns; the typical 295 / 595 ns pair lies inside the T63 windows (220-400 / 550-950 ns) and the T63 typicals (300 / 600 ns) lie inside the TX1812 windows, so one stream satisfies both printed sets. Supply, GRB framing and the other electrical tables are the same. Numbers only; no sheet relates the two, and nothing was measured.
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protocol compatible of this
TCWIN T80
T80 is the same 6028 footprint as TX1812DQ-F01 and its T0H / T1L windows equal the TX1812 ones; its T0L / T1H windows (545-1200 ns) contain the TX1812 typical 595 ns. Numbers only; nothing measured and no sheet relates the two.
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protocol compatible of this
TX1812CXA5
Same pin order, supply, 24-bit GRB framing and electrical table; only the printed timing windows differ (T0L/T1H 550-1200 ns here against 545-645 ns). The nominal values of the other TX1812 sheets (295 / 595 ns) lie inside these windows on T0H, T0L, T1H and T1L, so a stream built for those sheets is inside both sets of printed windows; the reverse is not true (900 ns is outside 545-645). Numbers only, never measured.
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protocol compatible of this
TX1813
Identical printed windows, supply range, drive-current options and 24-bit GRB framing; TX1813 adds the FDIN backup data input. Numbers only; the sheets never relate the two ICs. What FDIN does is not explained in any TX1813 sheet.
Library support
Not checked against FastLED’s chipset list or the other libraries’ source.
Parts using this protocol
Dating evidence
Evidence, not a release date. A library commit proves the part existed by that date and says nothing about how long before.
- 2023-03-22 datasheet revision TCWIN TX1812PXA5-F01 specification cover: date 20230322, version A1 (earliest TX1812 sheet held) ↗ day