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3.5 × 3.5 mm 6 pins top-emitting

TX1812H

3535 · smd · TX1812 · TCWIN

1-wire RGB 3.5–5.5 V active

At a glance

Colour
RGB8 bits per channel
Data
1-wiretimed pulses on one line
Supply
3.5–5.5 Vno backup data line
Size
3.5 × 3.5 × 1.4 mm6 pins · top
Max current
36 mA12 mA per channel
PWM
4 kHzreset 80 µs
Library support
FastLED WLED Adafruit

TX1812 in a six-pad 3.5 x 3.5 x 1.36 mm package. Pins (sheet p4-5): 1 GND, 2 NC (left floating on the PCB), 3 DIN, 4 VDD, 5 VDD (two supply pins that may be joined on the PCB), 6 DO. Pin 1 is at the polarity-marked bottom-right corner; numbering runs counter-clockwise. 12 mA per channel (9.6-14.4), cover rating 0.18 W, sheet version A2 dated 2023-03-27. The sheet text says the outline matches a “3838 LED” while the drawing, the title and LCSC all say 3.5 x 3.5 mm; filed here as 3535.

Datasheets disagree: the header of this sheet (and of the other 3535 6-pin TX1813/TX1818 sheets) names the package 3838 where its dimensions are 3.5 x 3.5 x 1.36 mm.

The three SKUs that LCSC lists as SMD3535-4P (HWBA-F01, HWCA-F02, EWCA-F10-E) are NOT filed here: LCSC calls them four-pin where this sheet is six-pin, and the letter E has no sheet. See tx1812-3535-4p.

Variants

One row per orderable SKU. Everything not listed is inherited from the part above.

Order codeFaceLensWhite PinsSiliconStatusFirst seenDatasheet
TX1812HLA-F01 — — — 6 — active 2023-03-27 A2
LCSC stock 0 when checked. LCSC stock 0 on 2026-10-15.

Pinout

TX1812HLA-F01
TX1812H 3535 package, top and side viewPin 1 is ringed. pin 1 GND (ground), pin 2 NC (no connect), pin 3 DIN (data in), pin 4 VDD (power), pin 5 VDD (power), pin 6 DO (data out).11 GNDground22 NCno connect33 DINdata in44 VDDpower55 VDDpower66 DOdata out3.5 mm3.5 mmtop view1.4 mmside view
  • Ground
  • No connect
  • Data
  • Power
  • Pin 1
  • Cut corner

Outline and pin positions checked against the manufacturer datasheet (C784555 TX1812HLA-F01 rev A2 p4). Pads 0.75 mm wide, 2.0 mm between inner edges; the three pads span 2.2 mm vertically (0.58 / 0.52 mm outer pads). Row pitch estimated. What this means.

  1. 1 GND ground
  2. 2 NC nc
  3. 3 DIN data in
  4. 4 VDD power
  5. 5 VDD power
  6. 6 DO data out

Protocol — TX1812

Timings shown from datasheet.

TX1812 bit timingTX1812 bit timing: a zero bit is 295 nanoseconds high then 595 low; a one bit is 595 high then 295 low; tolerance plus or minus 50 nanoseconds; reset 80 microseconds low1 · Bit encoding, to scaleDINhighlowbit 0 period 890 nsbit 1 period 890 nsT0H 295 ±50 nsT1H 595 ±50 nsT0L 595 ±50 nsT1L 295 ±50 ns"0" bit"1" bit02004006008001000120014001600time, ns± tolerance on each falling edge2 · One frame: 24 bits, most-significant bit firstDIN170110010007100110101700101100bitch 1 · 8 bitsch 2 · 8 bitsch 3 · 8 bitsChannel order not recorded for this protocol · frame = 24 × ~890 ns ≈ 21.4 µs · example data, first bits 1 0 1 …3 · RESET / latchlast bits of frame 1first bits of frame 2LEDs latch the data they receivedRESET: DIN low ≥ 80 µs (not to scale)4 · Cascade: each DOUT feeds the next DINMCULED 1DINDOUTLED 2DINDOUTLED NDINDOUTLED 1 keeps the first 24 bits, re-shapes the signal and sends the rest out on DOUT;LED 2 keeps the next 24, and so on. The last LED's DOUT is left unconnected.
T0H 295 / T0L 595 · T1H 595 / T1L 295 ns · ±50 ns · period 890 ns · reset 80 µs source: datasheet

Compatibility

  • protocol compatible of this TCWIN T62

    The T62 electrical and timing tables are word for word the TX1812 5 mA tables (windows, 3.5-5.5 V, 4 kV ESD, 5 mA, GRB). The T62 sheet never mentions TX1812; this edge is based on the identical numbers only.

  • protocol compatible of this TCWIN T63 group

    The TX1812 sheets print T0H 245-345 and T0L 545-645 ns; the typical 295 / 595 ns pair lies inside the T63 windows (220-400 / 550-950 ns) and the T63 typicals (300 / 600 ns) lie inside the TX1812 windows, so one stream satisfies both printed sets. Supply, GRB framing and the other electrical tables are the same. Numbers only; no sheet relates the two, and nothing was measured.

  • protocol compatible of this TCWIN T80

    T80 is the same 6028 footprint as TX1812DQ-F01 and its T0H / T1L windows equal the TX1812 ones; its T0L / T1H windows (545-1200 ns) contain the TX1812 typical 595 ns. Numbers only; nothing measured and no sheet relates the two.

  • protocol compatible of this TX1812CXA5

    Same pin order, supply, 24-bit GRB framing and electrical table; only the printed timing windows differ (T0L/T1H 550-1200 ns here against 545-645 ns). The nominal values of the other TX1812 sheets (295 / 595 ns) lie inside these windows on T0H, T0L, T1H and T1L, so a stream built for those sheets is inside both sets of printed windows; the reverse is not true (900 ns is outside 545-645). Numbers only, never measured.

  • protocol compatible of this TX1813

    Identical printed windows, supply range, drive-current options and 24-bit GRB framing; TX1813 adds the FDIN backup data input. Numbers only; the sheets never relate the two ICs. What FDIN does is not explained in any TX1813 sheet.

Dating evidence

Nobody announces these parts, so this records what we can actually cite rather than a release date. Library support proves only that the part existed by that date.

  • 2023-03-22 datasheet revision TCWIN TX1812PXA5-F01 specification cover: date 20230322, version A1 (earliest TX1812 sheet held) ↗ day
  • 2023-03-27 datasheet revision TCWIN TX1812HLA-F01 specification cover: date 20230327, version A2 ↗ day

Where to buy

Stub data — a few rows so purchase links can grow later. Prices are not tracked.

Similar parts

Same protocol or package first, then the same data scheme and colour channels.

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