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3.5 × 2.8 mm 4 pins top-emitting

TX1812D

3528 · smd · TX1812 · TCWIN

1-wire RGB 3.5–5.5 V active

At a glance

Colour
RGB8 bits per channel
Data
1-wiretimed pulses on one line
Supply
3.5–5.5 Vno backup data line
Size
3.5 × 2.8 × 1.8 mm4 pins · top
Max current
—per-channel not recorded
PWM
4 kHzreset 80 µs
Library support
FastLED WLED Adafruit

TX1812 in a 3528 package. The DLA5-F02 and DWBA-F01 sheets (version A2, 2023-03-27) show the same drawing: 3.5 x 2.8 x 1.75 mm with the leads included (3.2 mm body), pins 1 VDD, 2 DO, 3 GND, 4 DIN numbered counter-clockwise from top-left, chamfer at pin 3. The two sheets differ only in drive current: DLA5 5 mA (cover 0.08 W), DWBA 12 mA (9.6-14.4, cover 0.18 W). Timing is the common TX1812 window set.

The same footprint and pin order is used by TCWIN’s T67 and T68 (see tcwin-t67-3528 / tcwin-t68-3528), which carry different timing windows.

DWBA5-F02 and DWCA-F01 have no datasheet on LCSC; listed here by their shared IC code 1812 and package letter D, which is an inference. The “5” in DWBA5 matches the sheets where a trailing 5 goes with 5 mA (DLA5, CXA5, IXA5 and the Z5 sheet’s own statement “2020 built-in 5mA”) but that is a pattern, not a statement for this SKU.

Variants

One row per orderable SKU. Everything not listed is inherited from the part above.

Order codeFaceLensWhite PinsSiliconStatusFirst seenDatasheet
TX1812DLA5-F02 — — — 4 — active 2023-03-27 A2A2 ↗
5 mA per channel, cover rating 0.08 W. LCSC stock 10 when checked. LCSC stock 10 on 2026-10-15.
TX1812DWBA-F01 — — — 4 — active 2023-03-27 A2
12 mA per channel (9.6 / 12 / 14.4), cover rating 0.18 W. Sheet carries the newer letterhead (Tiancheng Hi-Tech (Shenzhen) Co., Ltd.). LCSC stock 2,640 on 2026-10-15.
TX1812DWBA5-F02 — — — 4 — active 2023-03-27 A2
No datasheet is listed on LCSC for this SKU. Package, pin order and drawing are taken from the sibling sheet TX1812DLA5-F02 and TX1812DWBA-F01 because both share IC code 1812 and package letter D; that is an inference from the part number, not something any sheet states. Drive current, timing window and the meaning of the remaining letters are not confirmed for this SKU. LCSC stock 1,940 on 2026-10-15.
TX1812DWCA-F01 — — — 4 — active 2023-03-27 A2
No datasheet is listed on LCSC for this SKU. Package, pin order and drawing are taken from the sibling sheet TX1812DWBA-F01 because both share IC code 1812 and package letter D; that is an inference from the part number, not something any sheet states. Drive current, timing window and the meaning of the remaining letters are not confirmed for this SKU. LCSC stock 2,110 on 2026-10-15.

Pinout

TX1812DLA5-F02TX1812DWBA-F01TX1812DWBA5-F02TX1812DWCA-F01
TX1812D 3528 package, top and side viewPin 1 is ringed. pin 1 VDD (power), pin 2 DO (data out), pin 3 GND (ground), pin 4 DIN (data in).11 VDDpower22 DOdata out33 GNDground44 DINdata in3.5 mm overall2.8 mmtop view1.8 mmside view
  • Power
  • Data
  • Ground
  • Pin 1
  • Cut corner

Outline and pin positions checked against the manufacturer datasheet (C27636977 TX1812DWBA-F01 rev A2 p4). Body 3.2 wide, 3.5 across the leads. Lead length and pitch read from the back view; the lead height (0.65 mm) is the land-pattern height and approximate. What this means.

  1. 1 VDD power
  2. 2 DO data out
  3. 3 GND ground
  4. 4 DIN data in

Protocol — TX1812

Timings shown from datasheet.

TX1812 bit timingTX1812 bit timing: a zero bit is 295 nanoseconds high then 595 low; a one bit is 595 high then 295 low; tolerance plus or minus 50 nanoseconds; reset 80 microseconds low1 · Bit encoding, to scaleDINhighlowbit 0 period 890 nsbit 1 period 890 nsT0H 295 ±50 nsT1H 595 ±50 nsT0L 595 ±50 nsT1L 295 ±50 ns"0" bit"1" bit02004006008001000120014001600time, ns± tolerance on each falling edge2 · One frame: 24 bits, most-significant bit firstDIN170110010007100110101700101100bitch 1 · 8 bitsch 2 · 8 bitsch 3 · 8 bitsChannel order not recorded for this protocol · frame = 24 × ~890 ns ≈ 21.4 µs · example data, first bits 1 0 1 …3 · RESET / latchlast bits of frame 1first bits of frame 2LEDs latch the data they receivedRESET: DIN low ≥ 80 µs (not to scale)4 · Cascade: each DOUT feeds the next DINMCULED 1DINDOUTLED 2DINDOUTLED NDINDOUTLED 1 keeps the first 24 bits, re-shapes the signal and sends the rest out on DOUT;LED 2 keeps the next 24, and so on. The last LED's DOUT is left unconnected.
T0H 295 / T0L 595 · T1H 595 / T1L 295 ns · ±50 ns · period 890 ns · reset 80 µs source: datasheet

Compatibility

  • protocol compatible of this TCWIN T62

    The T62 electrical and timing tables are word for word the TX1812 5 mA tables (windows, 3.5-5.5 V, 4 kV ESD, 5 mA, GRB). The T62 sheet never mentions TX1812; this edge is based on the identical numbers only.

  • protocol compatible of this TCWIN T63 group

    The TX1812 sheets print T0H 245-345 and T0L 545-645 ns; the typical 295 / 595 ns pair lies inside the T63 windows (220-400 / 550-950 ns) and the T63 typicals (300 / 600 ns) lie inside the TX1812 windows, so one stream satisfies both printed sets. Supply, GRB framing and the other electrical tables are the same. Numbers only; no sheet relates the two, and nothing was measured.

  • protocol compatible of this TCWIN T80

    T80 is the same 6028 footprint as TX1812DQ-F01 and its T0H / T1L windows equal the TX1812 ones; its T0L / T1H windows (545-1200 ns) contain the TX1812 typical 595 ns. Numbers only; nothing measured and no sheet relates the two.

  • protocol compatible of this TX1812CXA5

    Same pin order, supply, 24-bit GRB framing and electrical table; only the printed timing windows differ (T0L/T1H 550-1200 ns here against 545-645 ns). The nominal values of the other TX1812 sheets (295 / 595 ns) lie inside these windows on T0H, T0L, T1H and T1L, so a stream built for those sheets is inside both sets of printed windows; the reverse is not true (900 ns is outside 545-645). Numbers only, never measured.

  • protocol compatible of this TX1813

    Identical printed windows, supply range, drive-current options and 24-bit GRB framing; TX1813 adds the FDIN backup data input. Numbers only; the sheets never relate the two ICs. What FDIN does is not explained in any TX1813 sheet.

Dating evidence

Nobody announces these parts, so this records what we can actually cite rather than a release date. Library support proves only that the part existed by that date.

  • 2023-03-22 datasheet revision TCWIN TX1812PXA5-F01 specification cover: date 20230322, version A1 (earliest TX1812 sheet held) ↗ day
  • 2023-03-27 datasheet revision TCWIN TX1812DWBA-F01 specification cover: date 20230327, version A2 ↗ day
  • 2023-03-27 datasheet revision TCWIN TX1812DLA5-F02 specification cover: date 20230327, version A2 ↗ day

Where to buy

Stub data — a few rows so purchase links can grow later. Prices are not tracked.

Similar parts

Same protocol or package first, then the same data scheme and colour channels.

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