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TX1813

1-wire RGB · TCWIN · tx18xx

Channels
RGB
Bits / channel
8
Supply
3.5–5.5 V
PWM
4 kHz
Backup data
yes
Packages
5

The TX1812 timing with a backup data input (FDIN) on 5- and 6-pad packages: 6-pad 5050 (AXA), 6-pad 3535 (GLA), 5-pad 1515 (M5) and 5-pad 3010 (Y5). The sheets label the extra pin “backup data input” (on 3535 and 5050 also “cascade backup signal input” / “backup display signal input”) and say nothing more about its behaviour. The only TCWIN sheet that explains a backup port is TX1816ZLN-F01: “a backup communication port, so that when one chip in the cascade is damaged the following ones are not affected”. That explanation is NOT carried over here; whether TX1813’s FDIN works the same way (and how the pin should be wired in a chain) is unconfirmed.

12 mA per channel in the AXA / GLA packages (9.6-14.4 mA) and 5 mA in the M5 / Y5 packages.

Refresh & flicker

Same electrical table and 24-bit GRB framing as the TX1812 sheets, plus a second data input pin FDIN. Data rate 800 kHz typical; propagation delay at most 200 ns (TPLH / TPHL).

Timing

TX1813 bit timingTX1813 bit timing: a zero bit is 295 nanoseconds high then 595 low; a one bit is 595 high then 295 low; tolerance plus or minus 50 nanoseconds; reset 80 microseconds low1 · Bit encoding, to scaleDINhighlowbit 0 period 890 nsbit 1 period 890 nsT0H 295 ±50 nsT1H 595 ±50 nsT0L 595 ±50 nsT1L 295 ±50 ns"0" bit"1" bit02004006008001000120014001600time, ns± tolerance on each falling edge2 · One frame: 24 bits, most-significant bit firstDIN170110010007100110101700101100bitch 1 · 8 bitsch 2 · 8 bitsch 3 · 8 bitsChannel order not recorded for this protocol · frame = 24 × ~890 ns ≈ 21.4 µs · example data, first bits 1 0 1 …3 · RESET / latchlast bits of frame 1first bits of frame 2LEDs latch the data they receivedRESET: DIN low ≥ 80 µs (not to scale)4 · Cascade: each DOUT feeds the next DINMCULED 1DINDOUTLED 2DINDOUTLED NDINDOUTLED 1 keeps the first 24 bits, re-shapes the signal and sends the rest out on DOUT;LED 2 keeps the next 24, and so on. The last LED's DOUT is left unconnected.BIN (backup): tied to the previous pixel's DIN
T0H 295 / T0L 595 · T1H 595 / T1L 295 ns · ±50 ns · period 890 ns · reset 80 µs source: datasheet
SourceT0HT0LT1HT1LPeriodRateReset±
datasheet ↗ 295 ns 595 ns 595 ns 295 ns 890 ns 1124 kHz 80 µs 50 ns
Min/typ/max: T0H 245/295/345 ns, T0L 545/595/645 ns, T1H 545/595/645 ns, T1L 245/295/345 ns, reset at least 80 us; typicals recorded. The heading of this table in the AXA sheet reads “TH+TL=1.25 us + 600 ns” although the typical T0H + T0L is 890 ns; see tx1812 for the same window-versus-800 kHz question.

Clones & compatibility

“Compatible” is never stated bare here — each relationship carries how strong the claim is, and what bites if you assume too much.

  • protocol compatible TX1812

    Identical printed windows, supply range, drive-current options and 24-bit GRB framing; TX1813 adds the FDIN backup data input. Numbers only; the sheets never relate the two ICs. What FDIN does is not explained in any TX1813 sheet. source ↗

Library support

Not checked against FastLED’s chipset list or the other libraries’ source.

Parts using this protocol

Dating evidence

Evidence, not a release date. A library commit proves the part existed by that date and says nothing about how long before.

  • 2023-03-27 datasheet revision TCWIN TX1813AXA-F02 / GLA-F01 / M5 / Y5 specification covers: date 20230327, version A2 ↗ day