5.4 × 5.0 mm 6 pins top-emitting

TX1813A

5050 · smd · TX1813 · TCWIN

1-wire RGB 3.5–5.5 V backup data line active

At a glance

Colour
RGB8 bits per channel
Data
1-wiretimed pulses on one line
Supply
3.5–5.5 Vbackup data line
Size
5.4 × 5.0 × 1.6 mm6 pins · top
Max current
—per-channel not recorded
PWM
4 kHzreset 80 µs
Library support
FastLED WLED Adafruit

TX1813 (TX1812 timing plus a backup data input) in a six-pad 5050 package, 12 mA per channel (9.6-14.4), cover rating 0.18 W, sheet version A2 dated 2023-03-27. Pins (p5): 1 VDD, 2 VDD (each “connected with the other”), 3 DO, 4 DIN, 5 GND, 6 FDIN (backup data input). This is the only TCWIN 6-pin sheet whose numbering is not a ring: from the drawing, 1-2-3 run up the right column and 6-5-4 down the left (6 top-left, 4 bottom-left); the TX1818BJJ sheet (tx1818-5050-6p) numbers the same package counter-clockwise and puts different signals on the pins, so the two are not interchangeable.

The sheet does not explain what the backup input does; it is only labelled “backup data input”. The only TCWIN sheet that explains a backup port is TX1816ZLN-F01 (“the backup communication port lets a damaged chip in the cascade not affect the ones after it”); that statement is NOT carried over to TX1813 here.

Datasheets disagree with themselves: the heading of section 11 (p7) reads “TH+TL=1.25 us + 600 ns” while the table under it gives T0H 295 + T0L 595 = 890 ns typ; the same sheet’s data rate is 800 kHz typ (1.25 us). Section 14’s note reads “G7 -> BG … B0” (a typo for G7 -> G6).

TX1813AWCA-F02 has no datasheet on LCSC; listed by the shared IC code 1813 and package letter A (inference).

Variants

One row per orderable SKU. Everything not listed is inherited from the part above.

Order codeFaceLensWhite PinsSiliconStatusFirst seenDatasheet
TX1813AXA-F02 — — — 6 — active 2023-03-27 A2
12 mA per channel. LCSC stock 3,510 when checked. LCSC stock 3,510 on 2026-10-15.
TX1813AWCA-F02 — — — 6 — active 2023-03-27 A2
No datasheet is listed on LCSC for this SKU. Package, pin order and drawing are taken from the sibling sheet TX1813AXA-F02 because both share IC code 1813 and package letter A; that is an inference from the part number, not something any sheet states. Drive current, timing window and the meaning of the remaining letters are not confirmed for this SKU. LCSC stock 120 on 2026-10-15.

Pinout

TX1813AXA-F02TX1813AWCA-F02
TX1813A 5050 package, top and side viewPin 1 is ringed. pin 1 VDD (power), pin 2 VDD (power), pin 3 DO (data out), pin 4 DIN (data in), pin 5 GND (ground), pin 6 FDIN (backup in).11 VDDpower22 VDDpower33 DOdata out44 DINdata in55 GNDground66 FDINbackup in5.4 mm overall5.0 mmtop view1.6 mmside view
  • Power
  • Data
  • Ground
  • Backup data
  • Pin 1
  • Cut corner

Outline and pin positions checked against the manufacturer datasheet (C7495083 TX1813AXA-F02 rev A2 p4). Not a ring: the sheet numbers 1-2-3 up the right column and 4-5-6 up the left column (6 at top-left, 4 at bottom-left), unlike the other 6-pin TCWIN sheets. Pad heights are approximate. What this means.

  1. 1 VDD power
  2. 2 VDD power
  3. 3 DO data out
  4. 4 DIN data in
  5. 5 GND ground
  6. 6 FDIN backup data in

Protocol — TX1813

Timings shown from datasheet.

TX1813 bit timingTX1813 bit timing: a zero bit is 295 nanoseconds high then 595 low; a one bit is 595 high then 295 low; tolerance plus or minus 50 nanoseconds; reset 80 microseconds low1 · Bit encoding, to scaleDINhighlowbit 0 period 890 nsbit 1 period 890 nsT0H 295 ±50 nsT1H 595 ±50 nsT0L 595 ±50 nsT1L 295 ±50 ns"0" bit"1" bit02004006008001000120014001600time, ns± tolerance on each falling edge2 · One frame: 24 bits, most-significant bit firstDIN170110010007100110101700101100bitch 1 · 8 bitsch 2 · 8 bitsch 3 · 8 bitsChannel order not recorded for this protocol · frame = 24 × ~890 ns ≈ 21.4 µs · example data, first bits 1 0 1 …3 · RESET / latchlast bits of frame 1first bits of frame 2LEDs latch the data they receivedRESET: DIN low ≥ 80 µs (not to scale)4 · Cascade: each DOUT feeds the next DINMCULED 1DINDOUTLED 2DINDOUTLED NDINDOUTLED 1 keeps the first 24 bits, re-shapes the signal and sends the rest out on DOUT;LED 2 keeps the next 24, and so on. The last LED's DOUT is left unconnected.BIN (backup): tied to the previous pixel's DIN
T0H 295 / T0L 595 · T1H 595 / T1L 295 ns · ±50 ns · period 890 ns · reset 80 µs source: datasheet

Compatibility

  • protocol compatible TX1812

    Identical printed windows, supply range, drive-current options and 24-bit GRB framing; TX1813 adds the FDIN backup data input. Numbers only; the sheets never relate the two ICs. What FDIN does is not explained in any TX1813 sheet. source ↗

Dating evidence

Nobody announces these parts, so this records what we can actually cite rather than a release date. Library support proves only that the part existed by that date.

  • 2023-03-27 datasheet revision TCWIN TX1813AXA-F02 / GLA-F01 / M5 / Y5 specification covers: date 20230327, version A2 ↗ day

Where to buy

Stub data — a few rows so purchase links can grow later. Prices are not tracked.

Similar parts

Same protocol or package first, then the same data scheme and colour channels.

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