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TX1812CLL (RGBW)

1-wire RGBW · TCWIN · tx18xx

Channels
RGBW
Bits / channel
8
Supply
3.5–7.5 V
PWM
4 kHz
Backup data
no
Packages
1

TCWIN’s four-channel (RGBW) variant under the TX1812 number, described by its sheets as “a four-channel LED driver IC with MCU digital interface, data latch and LED drive”. 5 V supply (typical 5.0, absolute maximum 7.5 V), 0.7 VDD input-high threshold. Colour temperature of the white die printed as 6000-6500 K (FW601) and 8000-10000 K (FW802).

The T69 sheet (tcwin-t69) prints the same tables with different default currents (8 mA RGB, 16 mA W) and a 5700-6200 K white; the sheet does not name its IC.

Refresh & flicker

Four-channel driver: data order G, R, B, W, 32 bits per pixel, plus an optional 20-bit gain word (five bits per channel, GG/GR/GB/GW) that sets 2.4-39.6 mA per channel in 1.2 mA steps; default 12 mA. PWM 4 kHz, static 5 uA typical, delay at most 500 ns.

Timing

TX1812CLL (RGBW) bit timingTX1812CLL (RGBW) bit timing: a zero bit is 300 nanoseconds high then 900 low; a one bit is 900 high then 300 low; tolerance plus or minus 50 nanoseconds; reset 80 microseconds low1 · Bit encoding, to scaleDINhighlowbit 0 period 1200 nsbit 1 period 1200 nsT0H 300 ±50 nsT1H 900 ±50 nsT0L 900 ±50 nsT1L 300 ±50 ns"0" bit"1" bit020040060080010001200140016001800200022002400time, ns± tolerance on each falling edge2 · One frame: 32 bits, most-significant bit firstDIN1701100100071001101017001011001711000010bitch 1 · 8 bitsch 2 · 8 bitsch 3 · 8 bitsch 4 · 8 bitsChannel order not recorded for this protocol · frame = 32 × ~1200 ns ≈ 38.4 µs · example data, first bits 1 0 1 …3 · RESET / latchlast bits of frame 1first bits of frame 2LEDs latch the data they receivedRESET: DIN low ≥ 80 µs (not to scale)4 · Cascade: each DOUT feeds the next DINMCULED 1DINDOUTLED 2DINDOUTLED NDINDOUTLED 1 keeps the first 32 bits, re-shapes the signal and sends the rest out on DOUT;LED 2 keeps the next 32, and so on. The last LED's DOUT is left unconnected.
T0H 300 / T0L 900 · T1H 900 / T1L 300 ns · ±50 ns · period 1200 ns · reset 80 µs source: datasheet
SourceT0HT0LT1HT1LPeriodRateReset±
datasheet ↗ 300 ns 900 ns 900 ns 300 ns 1200 ns 833 kHz 80 µs 50 ns
Min/typ/max in microseconds: T0H 0.25/0.3/0.35, T0L 0.85/0.9/0.95, T1H 0.85/0.9/0.95, T1L 0.25/0.3/0.35, reset at least 80 us.

Clones & compatibility

“Compatible” is never stated bare here — each relationship carries how strong the claim is, and what bites if you assume too much.

  • protocol compatible of this TCWIN T69

    The T69 timing, voltage, thresholds, 32-bit GRBW frame and 20-bit gain table are identical to the TX1812CLL RGBW sheets; the defaults differ (R/G/B 8 mA, W 16 mA against 12 mA) and T69 adds a separate white supply pin VDDW. The T69 sheet does not mention TX1812. Numbers only.

Library support

Not checked against FastLED’s chipset list or the other libraries’ source.

Parts using this protocol

Dating evidence

Evidence, not a release date. A library commit proves the part existed by that date and says nothing about how long before.

  • 2023-02-25 datasheet revision TCWIN TX1812CLL-FW601 specification cover: date 20230225, version A2 (earliest TX1812 sheet held) ↗ day