5.4 × 5.0 mm 4 pins top-emitting

TX1812CLL

5050 · smd · TX1812CLL (RGBW) · TCWIN

1-wire RGBW 3.5–7.5 V active

At a glance

Colour
RGBW8 bits per channel
Data
1-wiretimed pulses on one line
Supply
3.5–7.5 Vno backup data line
Size
5.4 × 5.0 × 1.6 mm4 pins · top
Max current
—per-channel not recorded
PWM
4 kHzreset 80 µs
Library support
FastLED WLED Adafruit

Four-channel (RGBW) driver in a 5050 package. The sheet calls the IC a “four-channel LED driver IC” with an MCU digital interface, data latch and LED drive; GRBW data order, 32 bits per pixel plus an optional 20-bit gain word (five bits per channel, 2.4 mA to 39.6 mA in 1.2 mA steps). Default drive is 12 mA per channel; the sheet says the controller may omit the 20 gain bits when the 12 mA default is wanted. White channel 4-6 lm; the FW601 sheet prints colour temperature 6000-6500 K and the FW802 sheet 8000-10000 K. Pins 1 VDD, 2 DO, 3 GND, 4 DIN (same drawing as the RGB TX1812 5050 sheets). Supply: absolute 3.5-7.5 V, 5.0 V typical.

The FW802 sheet is a copy of the FW601 sheet with the title and the colour temperature (8000-10000 K) changed; both label the colour-temperature row with the symbol “W8”. The sheets do not say how the 3xx / 6xx / 8xx / 610 digits in the -FW suffix map to colour temperature beyond those two printed ranges.

The four CWBL-FW SKUs (FW301, FW601, FW610, FW802) have no datasheet on LCSC. They are placed here because their -FW suffix matches only this RGBW sheet family (no RGB sheet carries FW), but the third and fourth letters differ (CWBL against CLL), so channel count and colour temperature are an inference.

Variants

One row per orderable SKU. Everything not listed is inherited from the part above.

Order codeFaceLensWhite PinsSiliconStatusFirst seenDatasheet
TX1812CLL-FW601 — — — 4 — active 2023-02-25 A2
Sheet prints white 6000-6500 K, 4-6 lm at 12 mA. Cover date 2023-02-25, version A2, 0.2 W. LCSC stock 935 on 2026-10-15.
TX1812CLL-FW802 — — — 4 — active 2023-02-25 A2A2 ↗
Sheet is the FW601 sheet with the title and white colour temperature (8000-10000 K) changed. Cover date 2023-02-25, version A2. LCSC stock 695 on 2026-10-15.
TX1812CWBL-FW301 — — — 4 — active 2023-02-25 A2
No datasheet is listed on LCSC for this SKU. Package, pin order and drawing are taken from the sibling sheet TX1812CLL-FW601 and -FW802 because both share IC code 1812 and package letter C (suffix -FW); that is an inference from the part number, not something any sheet states. Drive current, timing window and the meaning of the remaining letters are not confirmed for this SKU. LCSC stock 995 on 2026-10-15.
TX1812CWBL-FW601 — — — 4 — active 2023-02-25 A2
No datasheet is listed on LCSC for this SKU. Package, pin order and drawing are taken from the sibling sheet TX1812CLL-FW601 because both share IC code 1812 and package letter C (suffix -FW601); that is an inference from the part number, not something any sheet states. Drive current, timing window and the meaning of the remaining letters are not confirmed for this SKU. LCSC stock 5 on 2026-10-15.
TX1812CWBL-FW610 — — — 4 — active 2023-02-25 A2
No datasheet is listed on LCSC for this SKU. Package, pin order and drawing are taken from the sibling sheet TX1812CLL-FW601 because both share IC code 1812 and package letter C (suffix -FW); that is an inference from the part number, not something any sheet states. Drive current, timing window and the meaning of the remaining letters are not confirmed for this SKU. LCSC stock 960 on 2026-10-15.
TX1812CWBL-FW802 — — — 4 — active 2023-02-25 A2
No datasheet is listed on LCSC for this SKU. Package, pin order and drawing are taken from the sibling sheet TX1812CLL-FW802 because both share IC code 1812 and package letter C (suffix -FW802); that is an inference from the part number, not something any sheet states. Drive current, timing window and the meaning of the remaining letters are not confirmed for this SKU. LCSC stock 0 on 2026-10-15.

Pinout

TX1812CLL-FW601TX1812CLL-FW802TX1812CWBL-FW301TX1812CWBL-FW601TX1812CWBL-FW610TX1812CWBL-FW802
TX1812CLL 5050 package, top and side viewPin 1 is ringed. pin 1 VDD (power), pin 2 DO (data out), pin 3 GND (ground), pin 4 DIN (data in).11 VDDpower22 DOdata out33 GNDground44 DINdata in5.4 mm overall5.0 mmtop view1.6 mmside view
  • Power
  • Data
  • Ground
  • Pin 1
  • Cut corner

Outline and pin positions checked against the manufacturer datasheet (C7495080 TX1812CLL-FW601 rev A2 p4). Pin 1 is top-left, numbering runs counter-clockwise, and the chamfer sits at pin 3 (GND), as in the WS2812B. The sheet marks "+" on the pin 1-2 side and "-" on the pin 3-4 side. Pad sizes read from the drawing; the part spans 5.4 mm across the leads. What this means.

  1. 1 VDD power
  2. 2 DO data out
  3. 3 GND ground
  4. 4 DIN data in

Protocol — TX1812CLL (RGBW)

Timings shown from datasheet.

TX1812CLL (RGBW) bit timingTX1812CLL (RGBW) bit timing: a zero bit is 300 nanoseconds high then 900 low; a one bit is 900 high then 300 low; tolerance plus or minus 50 nanoseconds; reset 80 microseconds low1 · Bit encoding, to scaleDINhighlowbit 0 period 1200 nsbit 1 period 1200 nsT0H 300 ±50 nsT1H 900 ±50 nsT0L 900 ±50 nsT1L 300 ±50 ns"0" bit"1" bit020040060080010001200140016001800200022002400time, ns± tolerance on each falling edge2 · One frame: 32 bits, most-significant bit firstDIN1701100100071001101017001011001711000010bitch 1 · 8 bitsch 2 · 8 bitsch 3 · 8 bitsch 4 · 8 bitsChannel order not recorded for this protocol · frame = 32 × ~1200 ns ≈ 38.4 µs · example data, first bits 1 0 1 …3 · RESET / latchlast bits of frame 1first bits of frame 2LEDs latch the data they receivedRESET: DIN low ≥ 80 µs (not to scale)4 · Cascade: each DOUT feeds the next DINMCULED 1DINDOUTLED 2DINDOUTLED NDINDOUTLED 1 keeps the first 32 bits, re-shapes the signal and sends the rest out on DOUT;LED 2 keeps the next 32, and so on. The last LED's DOUT is left unconnected.
T0H 300 / T0L 900 · T1H 900 / T1L 300 ns · ±50 ns · period 1200 ns · reset 80 µs source: datasheet

Compatibility

  • protocol compatible of this TCWIN T69

    The T69 timing, voltage, thresholds, 32-bit GRBW frame and 20-bit gain table are identical to the TX1812CLL RGBW sheets; the defaults differ (R/G/B 8 mA, W 16 mA against 12 mA) and T69 adds a separate white supply pin VDDW. The T69 sheet does not mention TX1812. Numbers only.

Dating evidence

Nobody announces these parts, so this records what we can actually cite rather than a release date. Library support proves only that the part existed by that date.

  • 2023-02-25 datasheet revision TCWIN TX1812CLL-FW601 specification cover: date 20230225, version A2 (earliest TX1812 sheet held) ↗ day
  • 2023-02-25 datasheet revision TCWIN TX1812CLL-FW802 specification cover: date 20230225, version A2 ↗ day

Where to buy

Stub data — a few rows so purchase links can grow later. Prices are not tracked.

Similar parts

Same protocol or package first, then the same data scheme and colour channels.

Was this page useful?

0 people found this useful