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WL-ICLED (24-bit single wire)

1-wire RGB · Wurth Elektronik · wl-icled

Channels
RGB
Bits / channel
8
Supply
3.3–5.5 V
PWM
5 kHz
Backup data
no
Packages
2

The single-wire WL-ICLED parts from Wurth Elektronik. Unusually for this catalogue the maker is a European passive-component house that publishes land patterns, MSL and a revision history, and sells through Digi-Key and Mouser rather than LCSC. The signalling is WS2812-like (24 bits, GRB, reshaping DOUT) but the IC is Wurth’s own and the timing is the symmetric 300/900 ns set, not the WS2812B’s 400/850.

Wurth uses three incompatible schemes under one brand: this one, the PLCC4 5050 revision wl-icled-p4, the 48-bit wl-icled-48, and the dual-wire wl-icled-spi. Check the order code, not the family name.

Refresh & flicker

PWM frequency 4-6 kHz (5 kHz typical) on the 2.0 mm and side-view parts. Propagation delay DIN to DOUT 80 ns either way, rise and fall 50 ns. Colour order on the wire is G, R, B, MSB first (the sheet’s bit-code tests light red with 0x00FF00).

Timing

WL-ICLED (24-bit single wire) bit timingWL-ICLED (24-bit single wire) bit timing: a zero bit is 300 nanoseconds high then 900 low; a one bit is 900 high then 300 low; tolerance plus or minus 150 nanoseconds; reset 200 microseconds low1 · Bit encoding, to scaleDINhighlowbit 0 period 1200 nsbit 1 period 1200 nsT0H 300 ±150 nsT1H 900 ±150 nsT0L 900 ±150 nsT1L 300 ±150 ns"0" bit"1" bit020040060080010001200140016001800200022002400time, ns± tolerance on each falling edge2 · One frame: 24 bits, most-significant bit firstDIN170110010007100110101700101100bitch 1 · 8 bitsch 2 · 8 bitsch 3 · 8 bitsChannel order not recorded for this protocol · frame = 24 × ~1200 ns ≈ 28.8 µs · example data, first bits 1 0 1 …3 · RESET / latchlast bits of frame 1first bits of frame 2LEDs latch the data they receivedRESET: DIN low ≥ 200 µs (not to scale)4 · Cascade: each DOUT feeds the next DINMCULED 1DINDOUTLED 2DINDOUTLED NDINDOUTLED 1 keeps the first 24 bits, re-shapes the signal and sends the rest out on DOUT;LED 2 keeps the next 24, and so on. The last LED's DOUT is left unconnected.
T0H 300 / T0L 900 · T1H 900 / T1L 300 ns · ±150 ns · period 1200 ns · reset 200 µs source: datasheet
SourceT0HT0LT1HT1LPeriodRateReset±
datasheet ↗ 300 ns 900 ns 900 ns 300 ns 1200 ns 833 kHz 200 µs 150 ns
Typical values; the sheet gives ranges: bit period 0.9-1.5 us, T0H and T1L 0.15-0.45 us, T0L and T1H 0.75-1.05 us. Reset is “200” in the Min column. Symmetric like the SK6812 and, like it, on a 1.2 us bit.

Clones & compatibility

“Compatible” is never stated bare here — each relationship carries how strong the claim is, and what bites if you assume too much.

  • protocol compatible SK6812

    On paper only: nominal 300/900/900/300 ns against the SK6812 datasheet's 300/900/600/600 and FastLED's 300/900/900/300, same GRB order, reset 200 us against the SK6812's 80 us (the current OPSCO sheet also says 200 us). No Wurth part has been driven from a SK6812 driver by this catalogue. source ↗

  • protocol compatible of this WL-ICLED (PLCC4 5050 timing)

    Same 24-bit GRB frame and nominal bit times. The datasheet windows, PWM frequency (2.5 kHz against 4-6 kHz), supply minimum (3.5 V against 3.3 V) and propagation delay differ, so Wurth treats them as separate silicon behaviours.

Library support

Parts using this protocol

Dating evidence

Evidence, not a release date. A library commit proves the part existed by that date and says nothing about how long before.

  • 2026-01-22 datasheet revision Wurth WL-ICLED 1312020030000 datasheet, revision 003.000 ↗ day