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WS2812D-V6

1-wire RGB · WorldSemi · ws281x · revision of WS2812B-V5

Channels
RGB
Bits / channel
8
Supply
3.3–5.3 V
PWM
2 kHz
Backup data
no
Packages
1

The timing class that the 5 mm and 8 mm through-hole WS2812D packages moved to with their V6 silicon, split out as a protocol because it changes the reset period. Listed on LCSC as WS2812D-F5-V6 and WS2812D-F8-V6.

Refresh & flicker

Datasheet: 2 kHz scan frequency, 800 kHz oscillator, at least 1024 pixels cascadable at 30 frames per second, static current below 1 uA, tolerant of reverse supply connection, 3.3 V supply supported. The V6 sheets give the logic-high threshold as 0.55 x VDD, lower than the 0.7 x VDD of the older WS2812D-F8 sheet, which is what lets them be driven from 3.3 V logic.

Timing

WS2812D-V6 bit timingWS2812D-V6 bit timing: a zero bit is 300 nanoseconds high then 875 low; a one bit is 875 high then 300 low; tolerance plus or minus 150 nanoseconds; reset 280 microseconds low1 · Bit encoding, to scaleDINhighlowbit 0 period 1175 nsbit 1 period 1175 nsT0H 300 ±150 nsT1H 875 ±150 nsT0L 875 ±150 nsT1L 300 ±150 ns"0" bit"1" bit02004006008001000120014001600180020002200time, ns± tolerance on each falling edge2 · One frame: 24 bits, most-significant bit firstDIN170110010007100110101700101100bitch 1 · 8 bitsch 2 · 8 bitsch 3 · 8 bitsChannel order not recorded for this protocol · frame = 24 × ~1175 ns ≈ 28.2 µs · example data, first bits 1 0 1 …3 · RESET / latchlast bits of frame 1first bits of frame 2LEDs latch the data they receivedRESET: DIN low ≥ 280 µs (not to scale)4 · Cascade: each DOUT feeds the next DINMCULED 1DINDOUTLED 2DINDOUTLED NDINDOUTLED 1 keeps the first 24 bits, re-shapes the signal and sends the rest out on DOUT;LED 2 keeps the next 24, and so on. The last LED's DOUT is left unconnected.
T0H 300 / T0L 875 · T1H 875 / T1L 300 ns · ±150 ns · period 1175 ns · reset 280 µs source: datasheet
SourceT0HT0LT1HT1LPeriodRateReset±
datasheet ↗ 300 ns 875 ns 875 ns 300 ns 1250 ns 800 kHz 280 µs 150 ns
Datasheet ranges, midpoints recorded here: T0H 220-380 ns, T1H 750 ns to 1 us, T0L 750 ns to 1 us, T1L 220-380 ns; reset is “280 us or more”. The midpoints are not figures WorldSemi states, they are the centres of its windows. Compare the original WS2812D-F8 sheet (ws2812b protocol), which gives 0.40 / 0.85 / 0.85 / 0.40 us +/-150 ns and a 50 us reset - the window moved and the reset grew fivefold, which is the same shift seen between the WS2812B and the WS2812B-V5.

Clones & compatibility

“Compatible” is never stated bare here — each relationship carries how strong the claim is, and what bites if you assume too much.

  • near clone WS2812B-V5

    Same 280 us reset, 2 kHz scan frequency and the same T0H window (220-380 ns) as the WS2812B-V5, whose sheet the catalogue now holds. The V6 dome's T1L window is SHORT (220-380 ns) where the V5's is 580 ns to 1 us (and its T1H and T0L windows are 750 ns to 1 us against the V5's 580 ns to 1 us), so it is not the same timing table. The windows overlap, so a V5 driver may work, but that is not a tested claim. source ↗

  • near clone WS2812B

    Through-hole four-leg pixel with the WS2812B command set, but the reset period is 280 us rather than 50 us. The datasheets for this family state the data order as RGB, where the WS2812B family is GRB; that statement has not been confirmed on a real part. source ↗

Library support

WLED
WS281x

No library names this silicon. It can be driven by the WS2812B or WS2812B-V5 chipset entries because the timing windows overlap; that is an inference from the datasheet windows, not a tested claim. The colour order the datasheet states (RGB) differs from the GRB the libraries default to, so expect to set the order by hand.

Parts using this protocol