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Xinglight 2812B 12 V 3535 (10.8-13.2 V, 9 mA)

1-wire RGB · Xinglight · xinglight

Channels
RGB
Bits / channel
8
Supply
10.8–13.2 V
PWM
4 kHz
Backup data
no
Packages
1

No datasheet names the driver IC or its maker: the sheets are Xinglight letterhead documents titled with the SKU only, so this protocol is defined by the figures the sheets print (supply, per-channel current, timing table, pin set), not by a known die.

Per-channel drive is 9 mA (feature list “preset 9 mA / channel”, electrical table 9 mA, optical test at IF = 9 mA); supply 10.8-13.2 V, 12 V nominal.

Datasheets disagree: the sheet is titled WS2812B-12V and uses the 0.25/0.58/1.0/0.4 us shape of the 5 V 0.25/0.47 us sheets, but the feature list says PWM scan 1.5 kHz while the table gives fPWM 4.0 kHz.

Refresh & flicker

fPWM 4.0 kHz (feature list: port scan 1.5 kHz), operating current 2.5 mA, VIH 3.5 V, VIL 1.0 V (3535-12V sheet C51900943).

Timing

Xinglight 2812B 12 V 3535 (10.8-13.2 V, 9 mA) bit timingXinglight 2812B 12 V 3535 (10.8-13.2 V, 9 mA) bit timing: a zero bit is 250 nanoseconds high then 1000 low; a one bit is 850 high then 400 low; reset 80 microseconds low1 · Bit encoding, to scaleDINhighlowbit 0 period 1250 nsbit 1 period 1250 nsT0H 250 nsT1H 850 nsT0L 1000 nsT1L 400 ns"0" bit"1" bit02505007501000125015001750200022502500time, ns2 · One frame: 24 bits, most-significant bit firstDIN170110010007100110101700101100bitch 1 · 8 bitsch 2 · 8 bitsch 3 · 8 bitsChannel order not recorded for this protocol · frame = 24 × ~1250 ns ≈ 30 µs · example data, first bits 1 0 1 …3 · RESET / latchlast bits of frame 1first bits of frame 2LEDs latch the data they receivedRESET: DIN low ≥ 80 µs (not to scale)4 · Cascade: each DOUT feeds the next DINMCULED 1DINDOUTLED 2DINDOUTLED NDINDOUTLED 1 keeps the first 24 bits, re-shapes the signal and sends the rest out on DOUT;LED 2 keeps the next 24, and so on. The last LED's DOUT is left unconnected.
T0H 250 / T0L 1000 · T1H 850 / T1L 400 ns · period 1250 ns · reset 80 µs source: datasheet
SourceT0HT0LT1HT1LPeriodRateReset±
datasheet ↗ 250 ns 1000 ns 850 ns 400 ns 1250 ns 800 kHz 80 µs —
Tin0h typ 0.25 us (no min or max), Tin1h 0.58/0.85/1.0 us, T0L typ 1.0, T1L typ 0.4, cycle min 1.2 typ 1.25 us, reset min 80 us. Same shape as the 0.25/0.47 us family.

Library support

Not checked against any library. The sheets state a 24-bit (32-bit for IC-01W) frame sent high bit first at 800 kbps.

Parts using this protocol

Dating evidence

Evidence, not a release date. A library commit proves the part existed by that date and says nothing about how long before.

  • 2025-12-30 estimate PDF CreationDate metadata of Xinglight sheet XL-3535RGBC-2812B-12V (LCSC C51900943); the sheet has no revision table, so this is only the date the PDF file was produced ↗ day