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Xinglight SK6812B 12 V 5050 (9-14 V, 8.5 mA, BIN)

1-wire RGB · Xinglight · xinglight

Channels
RGB
Bits / channel
8
Supply
9–14 V
PWM
8 kHz
Backup data
yes
Packages
1

No datasheet names the driver IC or its maker: the sheets are Xinglight letterhead documents titled with the SKU only, so this protocol is defined by the figures the sheets print (supply, per-channel current, timing table, pin set), not by a known die.

Datasheets disagree: note 1 says “when writing the program, the minimum code cycle is 0.9 us” while the table below it gives a minimum period of 1.2 us; the PWM is 8 kHz in the table but “signal cycle 4 ms” in the prose; the sheet is titled SK6812B yet its 12 V supply, 8.5 mA drive and 6-pin BIN/VDD1/VDD2 set resemble a backup-input 12 V pixel, not the 5 V SK6812.

Features claimed on p3: “intelligent reverse connection protection, components will not be damaged when 12V power supply is reversed” and “transmission distance of up to 5 m between points without extra circuit”. Neither tested.

Refresh & flicker

FPWM 8 kHz, static 0.5 mA, VIH 4 V, VIL 1 V, FOSC 800 kHz (max 1100 kHz), 4 kV ESD, propagation delay 200 ns max; prose says the PWM “signal cycle is 4 ms”.

Timing

Xinglight SK6812B 12 V 5050 (9-14 V, 8.5 mA, BIN) bit timingXinglight SK6812B 12 V 5050 (9-14 V, 8.5 mA, BIN) bit timing: a zero bit is 300 nanoseconds high then 900 low; a one bit is 900 high then 300 low; reset 200 microseconds low1 · Bit encoding, to scaleDINhighlowbit 0 period 1200 nsbit 1 period 1200 nsT0H 300 nsT1H 900 nsT0L 900 nsT1L 300 ns"0" bit"1" bit020040060080010001200140016001800200022002400time, ns2 · One frame: 24 bits, most-significant bit firstDIN170110010007100110101700101100bitch 1 · 8 bitsch 2 · 8 bitsch 3 · 8 bitsChannel order not recorded for this protocol · frame = 24 × ~1200 ns ≈ 28.8 µs · example data, first bits 1 0 1 …3 · RESET / latchlast bits of frame 1first bits of frame 2LEDs latch the data they receivedRESET: DIN low ≥ 200 µs (not to scale)4 · Cascade: each DOUT feeds the next DINMCULED 1DINDOUTLED 2DINDOUTLED NDINDOUTLED 1 keeps the first 24 bits, re-shapes the signal and sends the rest out on DOUT;LED 2 keeps the next 24, and so on. The last LED's DOUT is left unconnected.BIN (backup): tied to the previous pixel's DIN
T0H 300 / T0L 900 · T1H 900 / T1L 300 ns · period 1200 ns · reset 200 µs source: datasheet
SourceT0HT0LT1HT1LPeriodRateReset±
datasheet ↗ 300 ns 900 ns 900 ns 300 ns 1200 ns 833 kHz 200 µs —
Typical column: T0H 0.3, T0L 0.9, T1H 0.9, T1L 0.3 us, period min 1.2 us, Trst > 200 us; note 1 says the minimum code cycle is 0.9 us, note 2 that the low time must be under 20 us.

Clones & compatibility

“Compatible” is never stated bare here — each relationship carries how strong the claim is, and what bites if you assume too much.

  • protocol compatible SK6812

    Only the title says SK6812B. A 12 V (9-14 V) part with VDD1/VDD2 pins, 8.5 mA per channel, a BIN auxiliary input and "intelligent reverse connection protection"; the OPSCO SK6812 is a 5 V part. Nothing in the sheet states compatibility. source ↗

Library support

Not checked against any library. The sheets state a 24-bit (32-bit for IC-01W) frame sent high bit first at 800 kbps.

Parts using this protocol

Dating evidence

Evidence, not a release date. A library commit proves the part existed by that date and says nothing about how long before.

  • 2026-09-08 estimate PDF CreationDate metadata of Xinglight sheet XL-5050RGBC-SK6812B (LCSC C5349959); the sheet has no revision table, so this is only the date the PDF file was produced ↗ day