addressable.wiki

Yongyu 0.3 / 0.6 single-wire IC (BRG / RGB IC series)

1-wire RGB · Yongyu Photoelectric · yongyu

Channels
RGB
Bits / channel
8
Supply
3–7.5 V
PWM
4 kHz
Backup data
no
Packages
2

Yongyu’s ‘IC’ LED series. The part numbers read BRG (the 0807 and 1615 FI parts) or RGB (the FJ part) but every sheet says the data are sent in GRB order; datasheets disagree with their own part numbers, and with each other on the pin order: the 0807 sheets give 1 DOUT, 2 VDD, 3 DIN, 4 GND while the 1615 sheet gives 1 DIN, 2 GND, 3 DOUT, 4 VDD. The FJ sheet’s wavelength table also lists the green and blue rows with swapped values (G 460-475 nm, B 520-535 nm).

Refresh & flicker

Logic supply VDD 3.0-7.5 V (absolute maximum), chip supply 5 V typical, R/G/B output pin pressure 9 V, 800 kHz data rate (1100 kHz max), DIN to DOUT delay 500 ns, 24 bit per pixel sent G, R, B with the MSB first (‘Note: high bit first, in GRB order’), PWM about 4 kHz. Default drive 5 mA (FI) or 12 mA (FJ) per channel, default off at power-up. The ‘Light type’ line reads ‘scintillation - quick scintillation’ on all three sheets, but the sheet gives no pattern description.

Timing

Sources disagree. This is normal and worth understanding: FastLED's numbers are tuned to drive real parts reliably, including clones, while the datasheet gives the manufacturer's nominal figures. Both are recorded here rather than picking one and hiding the conflict.

Yongyu 0.3 / 0.6 single-wire IC (BRG / RGB IC series) bit timingYongyu 0.3 / 0.6 single-wire IC (BRG / RGB IC series) bit timing: a zero bit is 300 nanoseconds high then 600 low; a one bit is 600 high then 300 low; tolerance plus or minus 50 nanoseconds; reset 80 microseconds low1 · Bit encoding, to scaleDINhighlowbit 0 period 900 nsbit 1 period 900 nsT0H 300 ±50 nsT1H 600 ±50 nsT0L 600 ±50 nsT1L 300 ±50 ns"0" bit"1" bit020040060080010001200140016001800time, ns± tolerance on each falling edge2 · One frame: 24 bits, most-significant bit firstDIN170110010007100110101700101100bitch 1 · 8 bitsch 2 · 8 bitsch 3 · 8 bitsChannel order not recorded for this protocol · frame = 24 × ~900 ns ≈ 21.6 µs · example data, first bits 1 0 1 …3 · RESET / latchlast bits of frame 1first bits of frame 2LEDs latch the data they receivedRESET: DIN low ≥ 80 µs (not to scale)4 · Cascade: each DOUT feeds the next DINMCULED 1DINDOUTLED 2DINDOUTLED NDINDOUTLED 1 keeps the first 24 bits, re-shapes the signal and sends the rest out on DOUT;LED 2 keeps the next 24, and so on. The last LED's DOUT is left unconnected.
T0H 300 / T0L 600 · T1H 600 / T1L 300 ns · ±50 ns · period 900 ns · reset 80 µs source: datasheet
SourceT0HT0LT1HT1LPeriodRateReset±
datasheet ↗ 300 ns 600 ns 600 ns 300 ns 900 ns 1111 kHz 80 µs 50 ns
Both symbols take 0.9 us.
datasheet ↗ 295 ns 595 ns 595 ns 295 ns 890 ns 1124 kHz 80 µs 150 ns
Same split with a wider tolerance (+/-0.15 us).

Clones & compatibility

“Compatible” is never stated bare here — each relationship carries how strong the claim is, and what bites if you assume too much.

Library support

Not checked against FastLED, Adafruit or WLED source.

Parts using this protocol

Dating evidence

Evidence, not a release date. A library commit proves the part existed by that date and says nothing about how long before.

  • 2025-01-02 datasheet revision Yongyu YY-0807RGBJ26-07-FJ approval sheet, issue date 2025-1-2 (revision A.0) ↗ day