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Chongtian MX3 single-wire IC (0.295 / 0.595 us)

1-wire RGB · Chongtian · chongtian

Channels
RGB
Bits / channel
8
Supply
3.5–5.5 V
PWM
4.5 kHz
Backup data
no
Packages
1

A second Chongtian timing table, a symmetric 0.295 / 0.595 split with an 80 us reset, used for the 12 mA MX3 variants in the 2018 and 3227 packages. Treated as its own protocol because the timing differs from chongtian-m while the pin out and packages are the same.

Refresh & flicker

12 mA per channel on all MX3 sheets, 800 kbps, 256 levels. The datasheets disagree about the wire order: the CT-3227URGBC/H-P8 and /HW-P8 sheets (A1 2023-01-05) say ‘high bit first, in RGB order’, while the CT-3227UGRBC/HW-P8-MX3 (A2 2026-01-23) and CT-2018URGBC/H-P8-MX3 (A1 2023-01-05) sheets say GRB. Port PWM 4 kHz in the 3227 text (4.5 kHz table).

Timing

Chongtian MX3 single-wire IC (0.295 / 0.595 us) bit timingChongtian MX3 single-wire IC (0.295 / 0.595 us) bit timing: a zero bit is 295 nanoseconds high then 595 low; a one bit is 595 high then 295 low; tolerance plus or minus 50 nanoseconds; reset 80 microseconds low1 · Bit encoding, to scaleDINhighlowbit 0 period 890 nsbit 1 period 890 nsT0H 295 ±50 nsT1H 595 ±50 nsT0L 595 ±50 nsT1L 295 ±50 ns"0" bit"1" bit02004006008001000120014001600time, ns± tolerance on each falling edge2 · One frame: 24 bits, most-significant bit firstDIN170110010007100110101700101100bitch 1 · 8 bitsch 2 · 8 bitsch 3 · 8 bitsChannel order not recorded for this protocol · frame = 24 × ~890 ns ≈ 21.4 µs · example data, first bits 1 0 1 …3 · RESET / latchlast bits of frame 1first bits of frame 2LEDs latch the data they receivedRESET: DIN low ≥ 80 µs (not to scale)4 · Cascade: each DOUT feeds the next DINMCULED 1DINDOUTLED 2DINDOUTLED NDINDOUTLED 1 keeps the first 24 bits, re-shapes the signal and sends the rest out on DOUT;LED 2 keeps the next 24, and so on. The last LED's DOUT is left unconnected.
T0H 295 / T0L 595 · T1H 595 / T1L 295 ns · ±50 ns · period 890 ns · reset 80 µs source: datasheet
SourceT0HT0LT1HT1LPeriodRateReset±
datasheet ↗ 295 ns 595 ns 595 ns 295 ns 890 ns 1124 kHz 80 µs 50 ns
Both symbols take 0.89 us; no element-cycle row. The prose on the sheet says the reset is a low level of 80 us or more, matching the table.

Clones & compatibility

“Compatible” is never stated bare here — each relationship carries how strong the claim is, and what bites if you assume too much.

Library support

Not checked against FastLED, Adafruit or WLED source.

Parts using this protocol

Dating evidence

Evidence, not a release date. A library commit proves the part existed by that date and says nothing about how long before.

  • 2023-01-05 datasheet revision Chongtian CT-3227URGBC/H-P8 specification, 'Version A1, issue date 2023.01.05' ↗ day