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5.0 × 5.0 mm 6 pins top-emitting

APA102C

5050 · smd · APA102C · APA Electronic

SPI RGB 5–5.5 V active

Also sold as DotStar, APA102C 5050

At a glance

Colour
RGB8 bits per channel
Data
SPIclock + data, timing-tolerant
Supply
5–5.5 Vno backup data line
Size
5.0 × 5.0 × 1.4 mm6 pins · top
Max current ≠
60 mA20 mA per channel
PWM
20 kHzno reset period
Library support
FastLED WLED Adafruit

Datasheets disagree

The sources we hold state different values for the facts below. Rather than pick one quietly, both sides are listed with where each was read. Check the datasheet for the exact part number and revision you are buying. How this is shown.

This part, APA102C

Current per channel

The Shiji sheet’s feature list and its electrical table give different output currents.

What each source says about current per channel
SourceSaysPage
apa102c "Built-in 20 mA constant current output" 1
apa102c Sink current (RGB) 22.5 / 24.5 / 26.5 mA min / typ / max at VDD 5 V, VOL > 1 V 3

What we show. 20 mA is shown because the sheet’s own headline says so; the electrical table puts typical sink current nearer 24.5 mA. Design to the table and measure.

The cost-reduced APA102, and in practice what most “APA102” listings ship. Driven identically.

Variants

One row per orderable SKU. Everything not listed is inherited from the part above.

Order codeFaceLensWhite PinsSiliconStatusFirst seenDatasheet
APA102C white clear — 6 — active unknown PDF

Pinout

APA102C
APA102C 5050 package, top and side viewPin 1 is ringed. pin 1 SDI (data in), pin 2 CKI (clock in), pin 3 GND (ground), pin 4 VDD (power), pin 5 CKO (clock out), pin 6 SDO (data out).11 SDIdata in22 CKIclock in33 GNDground44 VDDpower55 CKOclock out66 SDOdata out5.4 mm overall5.0 mmtop view1.4 mmside view
  • Data
  • Clock
  • Ground
  • Power
  • Pin 1

Outline and pin positions checked against the manufacturer datasheet (Shiji / iPixel APA102C sheet p1-2). The sheet describes no chamfer or pin-1 mark. What this means.

  1. 1 SDI data in
  2. 2 CKI clock in
  3. 3 GND ground
  4. 4 VDD power
  5. 5 CKO clock out
  6. 6 SDO data out

Protocol — APA102C

This is an SPI part: the clock is explicit, so there is no fixed bit period. The frame layout is shown below.

APA102C SPI frameAPA102C clocked frame: start frame, one 32-bit LED frame per pixel with brightness and colour bytes, and an end frame, plus data and clock waveforms1 · Frame stream (data clocked on CLK)Start frame32 × 0LED 132 bitsLED 232 bits…LED N32 bitsEnd frameclock ≥ N/2 edgeseach LED forwards what it does not keep on DO / CO2 · One LED frame: 32 bits, MSB first111brightB 8G 8R 83 marker bits (111), 5-bit global brightness 0–31, then 8-bit channels3 · DATA and CLK, first 8 bits of an LED frameDATACLK11110010111 markerbrightness bits 4..0data changes while CLK is low,LED samples on the rising edgeno fixed bit period: clock rateis set by the host
Frame layout: APA102-family 32-bit LED frames convention, see the protocol notes for end-frame differences

Compatibility

  • drop in APA102

    A cost-reduced APA102 sold under a near-identical name. Driven identically; the difference is manufacturing, not protocol.

Similar parts

Same protocol or package first, then the same data scheme and colour channels.

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