addressable.wiki

APA102

SPI RGB · APA Electronic · apa102

Channels
RGB
Bits / channel
8
Supply
5–5.5 V
PWM
20 kHz
Backup data
no
Packages
3

The main SPI-driven alternative to the WS2812 family. Two wires instead of one, in exchange for timing that does not matter, very high PWM frequency, and a per-LED 5-bit global brightness field. The right choice when the processor is busy or a camera is pointed at it.

Refresh & flicker

~20 kHz PWM per cpldcpu’s teardown (the only source for the figure; the Shiji APA102C sheet held here lists a “refresh rate” of “400 cycle” and no PWM frequency; its electrical table gives the supply as 5.0 V typical and 5.5 V maximum, with no minimum, which is the 5.0-5.5 V range shown). High enough to be invisible to cameras, which is why these are the default choice for persistence-of-vision and film work. Note that reducing global brightness superimposes a much lower-frequency PWM, which can reintroduce visible flicker.

Frame format

APA102 SPI frameAPA102 clocked frame: start frame, one 32-bit LED frame per pixel with brightness and colour bytes, and an end frame, plus data and clock waveforms1 · Frame stream (data clocked on CLK)Start frame32 × 0LED 132 bitsLED 232 bits…LED N32 bitsEnd frameclock ≥ N/2 edgeseach LED forwards what it does not keep on DO / CO2 · One LED frame: 32 bits, MSB first111brightB 8G 8R 83 marker bits (111), 5-bit global brightness 0–31, then 8-bit channels3 · DATA and CLK, first 8 bits of an LED frameDATACLK11110010111 markerbrightness bits 4..0data changes while CLK is low,LED samples on the rising edgeno fixed bit period: clock rateis set by the host
Frame layout: APA102-family 32-bit LED frames convention, see the protocol notes for end-frame differences
SourceT0HT0LT1HT1LPeriodRateReset±
datasheet — — — — — — — —
Because the clock is explicit, timing is not critical and interrupts cannot corrupt a frame - the single biggest practical advantage over the WS2812 family.

Clones & compatibility

“Compatible” is never stated bare here — each relationship carries how strong the claim is, and what bites if you assume too much.

  • near clone SK9822

    Frequently sold as interchangeable and usually works, but the SK9822 implements global brightness as a real current source rather than superimposed PWM, runs a lower PWM frequency, updates non-staggered, and differs in end-frame handling. Not reliably drop-in. source ↗

  • protocol compatible of this ABOC HBGR32L two-wire IC (18 mA)

    The frame is APA102-shaped (32 zero bits, 111 + 5-bit brightness + three 8-bit values, 32 one bits) and the sheet shows the same SDI/CKI waveform. The two sheets disagree about the colour order, and neither names APA102, so only the frame structure is compared.

  • protocol compatible of this ABOC IC-NL3C-BA two-wire IC

    Same CIN/DIN clock-and-data arrangement and the same 32 zero-bit start frame, 3-bit '111' marker + 5-bit brightness and B, G, R order as APA102 on the page-4 description, but the sheet never mentions APA102 and gives no end-frame behaviour; recorded as a structural match.

  • drop in of this APA102C

    A cost-reduced APA102 sold under a near-identical name. Driven identically; the difference is manufacturing, not protocol.

  • drop in of this APA107

    Driven identically to the APA102 by every library. Marketed as a higher-refresh successor.

  • near clone of this HD107S

    Driven with the APA102 protocol by every library, and generally treated as a faster APA102. The caveat is that the specifications are vendor claims rather than a verifiable manufacturer datasheet, and the HD107S, APA107 and APA102 are frequently conflated in listings.

  • protocol compatible of this HD108

    Same SPI framing concept, but each pixel carries 16 bits per channel, so an APA102 driver will not produce correct output without explicit HD108 support.

  • protocol compatible of this H-Great P36 two-wire IC (15 MHz)

    Same 32 zero-bit start, '111' + 5-bit global brightness + B, G, R 8-bit command and the same separate clock / data wiring as APA102. The sleep command and the 15 MHz / 30 ns limits are extras with no APA102 counterpart on the sheet, and the sheet never names APA102.

  • protocol compatible of this Inolux PC (clock-and-data IC)

    Frame structure matches APA102 as drawn on the PC55 sheet p5: 32 zero bits start frame, per LED 32 bits '111' + 5-bit global brightness + Blue + Green + Red, 32 one bits end frame, clock and data on separate pins. The sheet never names APA102, so this is a structural match only; clock limits (30 MHz, 30 ns widths) and the end-frame behaviour have not been compared with the APA102 sheets.

  • electrically similar of this P9813

    Both are clock-plus-data chains with a 32-bit zero start frame and 32 bits per pixel in blue-green-red order, but the P9813 flag is two bits and is followed by inverted check bits rather than a 3-bit flag and 5-bit global brightness, so frames are not interchangeable.

  • near clone of this SK9822

    Widely sold as an APA102 equivalent and usually works, but it is not a drop-in. Global brightness is a controlled current source rather than superimposed PWM, so it does not flicker when dimmed. PWM is 4.7 kHz against 20 kHz. The update is non-staggered, and end-frame handling differs - a driver that relies on the APA102's end-frame behaviour can misbehave.

  • protocol compatible of this WL-ICLED (dual-wire)

    The frame layout reads like the APA102's: 32-bit zero start frame, 3 flag bits, 5-bit global brightness, blue-green-red 8-bit values, N/2 end bits. The differences on paper are the flag decoding (0b101 puts the LED to sleep) and the 300 ohm series resistors on both lines in the reference circuit. Nothing here has been run against an APA102 driver.

Library support

FastLED
APA102 ↗
Adafruit_DotStar
DOTSTAR_BGR
WLED
APA102

Sold by Adafruit as “DotStar”.

Parts using this protocol

Dating evidence

Evidence, not a release date. A library commit proves the part existed by that date and says nothing about how long before.

  • 2014-08-27 first documented cpldcpu, 'APA102 aka Superled' - the first detailed public analysis of the part ↗ day
  • 2014-11-30 first documented cpldcpu, 'Understanding the APA102 Superled' - full protocol and PWM teardown ↗ day
  • 2013-05-30 first library support FastLED — first commit introducing APA102 ↗ day
  • 2019-05-01 first library support WLED — first commit introducing APA102 ↗ day