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H-Great P36 two-wire IC (15 MHz)

SPI RGB · H-Great · hgreat

Channels
RGB
Bits / channel
8
Supply
3.5–5.5 V
PWM
—
Backup data
no
Packages
1

The H-Great P36 is an automotive-grade (AEC-Q102 qualification test guidelines) 3.6 x 3.5 x 1.47 mm RGB pixel with a 20 mA maximum output current per channel and 3.5-5.5 V supply. The IC is not named. Its datasheet is bilingual Chinese and English.

Refresh & flicker

32 consecutive zeros start a frame, then each LED takes a 32-bit command: bits [50:48] FLAG = 111, a 5-bit DIMMING field (32-level current control for all three channels), and 8-bit B, G, R grey scale (default 0). DIN is latched on the rising edge of CIN and the remaining command bits are passed on to the next LED. A sleep mode is entered by sending zero B, G, R together with flag 101 and dimming 00000 (written as 8b’A0); any new data wakes it within 1 ms, so the host should wait 1 ms before sending the next display command.

Frame format

H-Great P36 two-wire IC (15 MHz) SPI frameH-Great P36 two-wire IC (15 MHz) clocked frame: start frame, one 32-bit LED frame per pixel with brightness and colour bytes, and an end frame, plus data and clock waveforms1 · Frame stream (data clocked on CLK)Start frame32 × 0LED 132 bitsLED 232 bits…LED N32 bitsEnd frameclock ≥ N/2 edgeseach LED forwards what it does not keep on DO / CO2 · One LED frame: 32 bits, MSB first111brightch 1 8ch 2 8ch 3 83 marker bits (111), 5-bit global brightness 0–31, then 8-bit channels3 · DATA and CLK, first 8 bits of an LED frameDATACLK11110010111 markerbrightness bits 4..0data changes while CLK is low,LED samples on the rising edgeno fixed bit period: clock rateis set by the host
Frame layout: APA102-family 32-bit LED frames convention, see the protocol notes for end-frame differences
SourceT0HT0LT1HT1LPeriodRateReset±
datasheet ↗ — — — — — — — —
Clock and data: CIN frequency up to 15 MHz, CIN high and low pulse width >=30 ns, DIN to CIN set-up >=10 ns, hold >=5 ns, logic high 2.7 V min (VDD+0.4 max), low 0.4-1.0 V; DOUT/COUT output high >=4.5 V, low <=0.4 V, standby (sleep) current 1 uA typ.

Clones & compatibility

“Compatible” is never stated bare here — each relationship carries how strong the claim is, and what bites if you assume too much.

  • protocol compatible APA102

    Same 32 zero-bit start, '111' + 5-bit global brightness + B, G, R 8-bit command and the same separate clock / data wiring as APA102. The sleep command and the 15 MHz / 30 ns limits are extras with no APA102 counterpart on the sheet, and the sheet never names APA102. source ↗

Library support

Not checked against FastLED, Adafruit or WLED source.

Parts using this protocol

Dating evidence

Evidence, not a release date. A library commit proves the part existed by that date and says nothing about how long before.

  • 2023-07-28 datasheet revision H-Great P36-RGB05P05N3P1INA03-CC sheet, page 1 'Version A0 2023-07-28' (page footer later reads A2 2024-9-2) ↗ day