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Inolux PC (clock-and-data IC)

SPI RGB · Inolux Corporation · inolux

Channels
RGB
Bits / channel
8
Supply
4.5–5.5 V
PWM
1.2 kHz
Backup data
no
Packages
2

Inolux’s two-wire part: SDI/CKI in, SDO/CKO out, ‘5Bit (32) to adjust the brightness’ and ‘8Bit (256) colour’. The key on the sheets lists ‘PC - Clock Function IC’ next to ‘PI - Single trace IC’. Datasheet disagreement: the PC55 ‘Pin Configuration’ table names pin 6 SDO ‘Data Input’ in the Pin Name column although its function text says ‘control signal output data’.

Refresh & flicker

SDI is read on the rising edge of CKI; the PC20 sheet adds that SDI changes on the falling edge and SDO changes on the rising edge, so CKO must be staggered half a clock against CKI for a chain to work. PWM 1.2 kHz (PC55) or 4 kHz (PC20), 256 grey levels per channel plus a 5-bit (32 level) global brightness field; the IC sets all three channels from it.

Frame format

Inolux PC (clock-and-data IC) SPI frameInolux PC (clock-and-data IC) clocked frame: start frame, one 32-bit LED frame per pixel with brightness and colour bytes, and an end frame, plus data and clock waveforms1 · Frame stream (data clocked on CLK)Start frame32 × 0LED 132 bitsLED 232 bits…LED N32 bitsEnd frameclock ≥ N/2 edgeseach LED forwards what it does not keep on DO / CO2 · One LED frame: 32 bits, MSB first111brightch 1 8ch 2 8ch 3 83 marker bits (111), 5-bit global brightness 0–31, then 8-bit channels3 · DATA and CLK, first 8 bits of an LED frameDATACLK11110010111 markerbrightness bits 4..0data changes while CLK is low,LED samples on the rising edgeno fixed bit period: clock rateis set by the host
Frame layout: APA102-family 32-bit LED frames convention, see the protocol notes for end-frame differences
SourceT0HT0LT1HT1LPeriodRateReset±
datasheet ↗ — — — — — — — —
SPI-style: no bit timing. PC55: clock high and low width >30 ns, data set-up >10 ns, maximum serial clock 30 MHz (‘The maximum frequency of 30MHZ serial data input’). PC20: clock high / low 17 ns typical, set-up 10 ns max. Frame rate = 1 / ((64 + 32 x points) x CKI period): 1024 LEDs at a 1 MHz clock gives 30 frames per second.

Clones & compatibility

“Compatible” is never stated bare here — each relationship carries how strong the claim is, and what bites if you assume too much.

  • protocol compatible APA102

    Frame structure matches APA102 as drawn on the PC55 sheet p5: 32 zero bits start frame, per LED 32 bits '111' + 5-bit global brightness + Blue + Green + Red, 32 one bits end frame, clock and data on separate pins. The sheet never names APA102, so this is a structural match only; clock limits (30 MHz, 30 ns widths) and the end-frame behaviour have not been compared with the APA102 sheets. source ↗

Library support

Not checked against FastLED, Adafruit or WLED source.

Parts using this protocol

Dating evidence

Evidence, not a release date. A library commit proves the part existed by that date and says nothing about how long before.

  • 2018-06-30 datasheet revision Inolux IN-PC55TBTRGB revision table: 'Initial Release 1.0 06-30-2018' ↗ day