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2.0 × 2.0 mm 6 pins top-emitting

IN-PC20TBT5R5G5B

2020 · smd · Inolux PC (clock-and-data IC) · Inolux Corporation

SPI RGB 4.5–5.5 V active

Also sold as IN-PC20TBT5R5G5B

At a glance

Colour
RGB8 bits per channel
Data
SPIclock + data, timing-tolerant
Supply
4.5–5.5 Vno backup data line
Size
2.0 × 2.0 × 0.7 mm6 pins · top
Max current
15 mA5 mA per channel
PWM
1.2 kHzno reset period
Library support
FastLED WLED Adafruit

Inolux’s 2020 clock-and-data pixel. The sheet title for its ‘2.02.00.65 mm’ body copies the PI20TB text but with six pins and a different pin order from the PI20TB. Absolute maximum VDD 3.7-5.5 V; clock high / low width 17 ns, set-up 10 ns; 4 kHz PWM. LCSC stock 16 on 2026-10-15.

Variants

One row per orderable SKU. Everything not listed is inherited from the part above.

Order codeFaceLensWhite PinsSiliconStatusFirst seenDatasheet
IN-PC20TBT5R5G5B — — — 6 — active 2020-03-20 1.1
LCSC C21468197, stock 16.

Pinout

IN-PC20TBT5R5G5B
IN-PC20TBT5R5G5B 2020 package, top and side viewPin 1 is ringed. pin 1 SDO (data out), pin 2 GND (ground), pin 3 SDI (data in), pin 4 CKI (clock in), pin 5 VDD (power), pin 6 CKO (clock out).11 SDOdata out22 GNDground33 SDIdata in44 CKIclock in55 VDDpower66 CKOclock out2.0 mm2.0 mmtop view0.7 mmside view
  • Data
  • Ground
  • Clock
  • Power
  • Pin 1

Outline and pin positions checked against the manufacturer datasheet (C21468197 IN-PC20TBT5R5G5B v1.1 p1-2). Pads 0.70 x 0.40 mm with a 0.60 mm column gap and three rows, from the top-view PCB figure; the numbered figure runs 1 SDO top-left down to 3 SDI bottom-left, then 4 CKI bottom-right up to 6 CKO top-right. What this means.

  1. 1 SDO data out
  2. 2 GND ground
  3. 3 SDI data in
  4. 4 CKI clock in
  5. 5 VDD power
  6. 6 CKO clock out

Protocol — Inolux PC (clock-and-data IC)

This is an SPI part: the clock is explicit, so there is no fixed bit period. The frame layout is shown below.

Inolux PC (clock-and-data IC) SPI frameInolux PC (clock-and-data IC) clocked frame: start frame, one 32-bit LED frame per pixel with brightness and colour bytes, and an end frame, plus data and clock waveforms1 · Frame stream (data clocked on CLK)Start frame32 × 0LED 132 bitsLED 232 bits…LED N32 bitsEnd frameclock ≥ N/2 edgeseach LED forwards what it does not keep on DO / CO2 · One LED frame: 32 bits, MSB first111brightch 1 8ch 2 8ch 3 83 marker bits (111), 5-bit global brightness 0–31, then 8-bit channels3 · DATA and CLK, first 8 bits of an LED frameDATACLK11110010111 markerbrightness bits 4..0data changes while CLK is low,LED samples on the rising edgeno fixed bit period: clock rateis set by the host
Frame layout: APA102-family 32-bit LED frames convention, see the protocol notes for end-frame differences

Compatibility

  • protocol compatible APA102

    Frame structure matches APA102 as drawn on the PC55 sheet p5: 32 zero bits start frame, per LED 32 bits '111' + 5-bit global brightness + Blue + Green + Red, 32 one bits end frame, clock and data on separate pins. The sheet never names APA102, so this is a structural match only; clock limits (30 MHz, 30 ns widths) and the end-frame behaviour have not been compared with the APA102 sheets. source ↗

Dating evidence

Nobody announces these parts, so this records what we can actually cite rather than a release date. Library support proves only that the part existed by that date.

  • 2018-06-30 datasheet revision Inolux IN-PC55TBTRGB revision table: 'Initial Release 1.0 06-30-2018' ↗ day
  • 2020-03-20 datasheet revision Inolux IN-PC20TBT5R5G5B revision table: 'Initial Release 1.0 03-20-2020' ↗ day

Where to buy

Stub data — a few rows so purchase links can grow later. Prices are not tracked.

Similar parts

Same protocol or package first, then the same data scheme and colour channels.

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