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5.0 × 5.0 mm 6 pins top-emitting

IN-PC55TBTRGB

5050 · smd · Inolux PC (clock-and-data IC) · Inolux Corporation

SPI RGB 4.5–5.5 V active

Also sold as IN-PC55TBTRGB

At a glance

Colour
RGB8 bits per channel
Data
SPIclock + data, timing-tolerant
Supply
4.5–5.5 Vno backup data line
Size
5.0 × 5.0 × 1.6 mm6 pins · top
Max current
60 mA20 mA per channel
PWM
1.2 kHzno reset period
Library support
FastLED WLED Adafruit

Datasheets disagree: the title and description say 5.0 x 5.0 x 1.6 mm, but the label-specification key on the same sheet gives ‘55TB = 5.5 x 5.5 x 1.6 mm, 6 pins’. The drawing shows 5.0 mm. Absolute maximum VDD -0.5 to +5.5 V with a typical 5.0 V (max 5.3 V), operating -20 to +80 C, ESD 4 kV, PWM 1.2 kHz, 1 mA static. Colour order on the wire: B, G, R (frame as in the protocol note). LCSC stock 0 on 2026-10-15.

Variants

One row per orderable SKU. Everything not listed is inherited from the part above.

Order codeFaceLensWhite PinsSiliconStatusFirst seenDatasheet
IN-PC55TBTRGB — — — 6 — active 2018-06-30 1.1
LCSC C2891911, stock 0.

Pinout

IN-PC55TBTRGB
IN-PC55TBTRGB 5050 package, top and side viewPin 1 is ringed. pin 1 SDI (data in), pin 2 CKI (clock in), pin 3 GND (ground), pin 4 VCC (power), pin 5 CKO (clock out), pin 6 SDO (data out).11 SDIdata in22 CKIclock in33 GNDground44 VCCpower55 CKOclock out66 SDOdata out5.4 mm overall5.0 mmtop view1.6 mmside view
  • Data
  • Clock
  • Ground
  • Power
  • Pin 1
  • Cut corner

Outline and pin positions checked against the manufacturer datasheet (C2891911 IN-PC55TBTRGB v1.1 p1-2). Six 1.0 x 1.0 mm pads, 5.4 mm across, 4.2 mm tall, pin 1 bottom-right (cut corner). What this means.

  1. 1 SDI data in
  2. 2 CKI clock in
  3. 3 GND ground
  4. 4 VCC power
  5. 5 CKO clock out
  6. 6 SDO data out

Protocol — Inolux PC (clock-and-data IC)

This is an SPI part: the clock is explicit, so there is no fixed bit period. The frame layout is shown below.

Inolux PC (clock-and-data IC) SPI frameInolux PC (clock-and-data IC) clocked frame: start frame, one 32-bit LED frame per pixel with brightness and colour bytes, and an end frame, plus data and clock waveforms1 · Frame stream (data clocked on CLK)Start frame32 × 0LED 132 bitsLED 232 bits…LED N32 bitsEnd frameclock ≥ N/2 edgeseach LED forwards what it does not keep on DO / CO2 · One LED frame: 32 bits, MSB first111brightch 1 8ch 2 8ch 3 83 marker bits (111), 5-bit global brightness 0–31, then 8-bit channels3 · DATA and CLK, first 8 bits of an LED frameDATACLK11110010111 markerbrightness bits 4..0data changes while CLK is low,LED samples on the rising edgeno fixed bit period: clock rateis set by the host
Frame layout: APA102-family 32-bit LED frames convention, see the protocol notes for end-frame differences

Compatibility

  • protocol compatible APA102

    Frame structure matches APA102 as drawn on the PC55 sheet p5: 32 zero bits start frame, per LED 32 bits '111' + 5-bit global brightness + Blue + Green + Red, 32 one bits end frame, clock and data on separate pins. The sheet never names APA102, so this is a structural match only; clock limits (30 MHz, 30 ns widths) and the end-frame behaviour have not been compared with the APA102 sheets. source ↗

Dating evidence

Nobody announces these parts, so this records what we can actually cite rather than a release date. Library support proves only that the part existed by that date.

  • 2018-06-30 datasheet revision Inolux IN-PC55TBTRGB revision table: 'Initial Release 1.0 06-30-2018' ↗ day

Where to buy

Stub data — a few rows so purchase links can grow later. Prices are not tracked.

Similar parts

Same protocol or package first, then the same data scheme and colour channels.

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