2.0 × 1.7 mm — pins top-emitting

T64

2017 · smd · TCWIN T64 · TCWIN

1-wire RGB 3.5–5.5 V active

At a glance

Colour
RGB8 bits per channel
Data
1-wiretimed pulses on one line
Supply
3.5–5.5 Vno backup data line
Size
2.0 × 1.7 × 0.8 mm— pins · top
Max current
15 mA5 mA per channel
PWM
4 kHzreset 80 µs
Library support
FastLED WLED Adafruit

TCWIN T64: a 2.0 x 1.7 x 0.85 mm built-in-IC LED, 5 mA per channel, version A1 dated 2025-04-15. Pinout deliberately left unknown.

Datasheets disagree with themselves: the drawing on page 4 (copied from T63/T65) labels 1 DO, 2 GND, 3 DIN, 4 VDD, while the pin table on page 5 lists 1 VDD, 2 DIN, 3 GND, 4 DO - the pin order of the 1010 T62. Both cannot be right for the same four pads and nothing in the sheet says which is current. If the table is right it is the T62 scheme (VDD, DIN, GND, DO) applied to a 2017 body; if the drawing is right it is the T63/T65 scheme. Not checked on hardware. T64 also differs electrically from T63: 6 kV ESD, 60 uA static current, 150 ns propagation delay and a printed logic-input range of 3-5.5 V.

Variants

One row per orderable SKU. Everything not listed is inherited from the part above.

Order codeFaceLensWhite PinsSiliconStatusFirst seenDatasheet
T64 — — — — — active 2025-04-15 A1
LCSC stock 1,130 on 2026-10-15.

Protocol — TCWIN T64

Timings shown from datasheet.

TCWIN T64 bit timingTCWIN T64 bit timing: a zero bit is 300 nanoseconds high then 600 low; a one bit is 600 high then 300 low; reset 80 microseconds low1 · Bit encoding, to scaleDINhighlowbit 0 period 900 nsbit 1 period 900 nsT0H 300 nsT1H 600 nsT0L 600 nsT1L 300 ns"0" bit"1" bit020040060080010001200140016001800time, ns2 · One frame: 24 bits, most-significant bit firstDIN170110010007100110101700101100bitch 1 · 8 bitsch 2 · 8 bitsch 3 · 8 bitsChannel order not recorded for this protocol · frame = 24 × ~900 ns ≈ 21.6 µs · example data, first bits 1 0 1 …3 · RESET / latchlast bits of frame 1first bits of frame 2LEDs latch the data they receivedRESET: DIN low ≥ 80 µs (not to scale)4 · Cascade: each DOUT feeds the next DINMCULED 1DINDOUTLED 2DINDOUTLED NDINDOUTLED 1 keeps the first 24 bits, re-shapes the signal and sends the rest out on DOUT;LED 2 keeps the next 24, and so on. The last LED's DOUT is left unconnected.
T0H 300 / T0L 600 · T1H 600 / T1L 300 ns · period 900 ns · reset 80 µs source: datasheet

Dating evidence

Nobody announces these parts, so this records what we can actually cite rather than a release date. Library support proves only that the part existed by that date.

  • 2025-04-15 datasheet revision TCWIN T64 specification cover: date 20250415, version A1 ↗ day

Where to buy

Stub data — a few rows so purchase links can grow later. Prices are not tracked.

Similar parts

Same protocol or package first, then the same data scheme and colour channels.

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