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Harvatek T4213

1-wire RGB · Harvatek · harvatek

Channels
RGB
Bits / channel
8
Supply
3.3–6 V
PWM
3.6 kHz
Backup data
no
Packages
2

A Taiwanese LED packager’s own IC, with a feature the WS2812 family lacks: timing is specified as a pulse-width threshold and the allowed bit period spans a 2:1 range. Both sheets are Preliminary and both name the IC “T4213” in the same text, even the 3.7 x 3.5 mm one whose part number starts T37.

Refresh & flicker

PWM 3.6 kHz, data rate 800 kHz, propagation delay 130 ns, 12 mA sink current per channel. GRB order, MSB first. Both datasheets are marked Preliminary.

Timing

Harvatek T4213 bit timingHarvatek T4213 bit timing: a zero bit is 305 nanoseconds high then 945 low; a one bit is 610 high then 640 low; reset 200 microseconds low1 · Bit encoding, to scaleDINhighlowbit 0 period 1250 nsbit 1 period 1250 nsT0H 305 nsT1H 610 nsT0L 945 nsT1L 640 ns"0" bit"1" bit02505007501000125015001750200022502500time, ns2 · One frame: 24 bits, most-significant bit firstDIN170110010007100110101700101100bitch 1 · 8 bitsch 2 · 8 bitsch 3 · 8 bitsChannel order not recorded for this protocol · frame = 24 × ~1250 ns ≈ 30 µs · example data, first bits 1 0 1 …3 · RESET / latchlast bits of frame 1first bits of frame 2LEDs latch the data they receivedRESET: DIN low ≥ 200 µs (not to scale)4 · Cascade: each DOUT feeds the next DINMCULED 1DINDOUTLED 2DINDOUTLED NDINDOUTLED 1 keeps the first 24 bits, re-shapes the signal and sends the rest out on DOUT;LED 2 keeps the next 24, and so on. The last LED's DOUT is left unconnected.
T0H 305 / T0L 945 · T1H 610 / T1L 640 ns · period 1250 ns · reset 200 µs source: datasheet
SourceT0HT0LT1HT1LPeriodRateReset±
datasheet ↗ 305 ns — 610 ns — 1250 ns 800 kHz 200 µs —
Only the HIGH times are specified: T0H typical 305 ns (350 max), T1H typical 610 ns (540 min), bit period typical 1250 ns. The sheet says the part accepts a bit period from 1.25 us (800 kHz) to 2.5 us (400 kHz), so the low times are whatever fills the period; they are null here because the sheet gives none. Reset is more than 200 us low. Between bytes the low time must stay under 50 us or the chip mis-resets.

Clones & compatibility

“Compatible” is never stated bare here — each relationship carries how strong the claim is, and what bites if you assume too much.

  • electrically similar WS2812B

    Same 24-bit GRB frame and an 800 kHz bit rate, but the chip decides a bit by the length of its HIGH pulse alone (350 ns or less is a zero, 540 ns or more is a one) and tolerates bit periods up to 2.5 us. A WS2812B driver may work; the 200 us reset and the 50 us inter-byte limit are the traps. Not tested. source ↗

Library support

Parts using this protocol

Dating evidence

Evidence, not a release date. A library commit proves the part existed by that date and says nothing about how long before.

  • 2025-05-09 datasheet revision Harvatek T37G3GRB-12C0001X2U1930 datasheet (Preliminary) ↗ day