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3.7 × 3.5 mm 4 pins top-emitting

T37G3GRB-12C0001X2U1930

3735 · smd · Harvatek T4213 · Harvatek

1-wire RGB 3.3–6 V unknown

Also sold as T37G3GRB

At a glance

Colour
RGB8 bits per channel
Data
1-wiretimed pulses on one line
Supply
3.3–6 Vno backup data line
Size
3.7 × 3.5 × 0.9 mm4 pins · top
Max current
36 mA12 mA per channel
PWM
3.6 kHzreset 200 µs
Library support
FastLED WLED Adafruit

Harvatek’s SK6812MINI-shaped part: the same 3.7 x 3.5 mm outline and pin order (1 DI, 2 VDD, 3 DO, 4 GND) as the OPSCO 3535 MINI, with a different IC whose timing only specifies the high times (see the protocol page). Status is unknown because the sheet is marked Preliminary and no distributor stock was checked.

Variants

One row per orderable SKU. Everything not listed is inherited from the part above.

Order codeFaceLensWhite PinsSiliconStatusFirst seenDatasheet
T37G3GRB-12C0001X2U1930 — clear — 4 — unknown 2025-05-09 Preliminary
Lens colour is not stated in the sheet; clear is inferred from the drawing and should be checked.

Pinout

T37G3GRB-12C0001X2U1930
T37G3GRB-12C0001X2U1930 3735 package, top and side viewPin 1 is ringed. pin 1 DI (data in), pin 2 VDD (power), pin 3 DO (data out), pin 4 GND (ground).11 DIdata in22 VDDpower33 DOdata out44 GNDground3.5 mm3.5 mmtop view0.9 mmside view
  • Data
  • Power
  • Ground
  • Pin 1
  • Cut corner

Outline and pin positions checked against the manufacturer datasheet (Harvatek T37G3GRB sheet (Preliminary, 2025-05-09) p4: pin 1 DI top-left, 2 VDD bottom-left, 3 DO bottom-right, 4 GND top-right). The asymmetric pad widths (1.2 / 2.05 / 2.1 / 1.15 mm) match the SK6812MINI template. What this means.

  1. 1 DI data in
  2. 2 VDD power
  3. 3 DO data out
  4. 4 GND ground

Protocol — Harvatek T4213

Timings shown from datasheet.

Harvatek T4213 bit timingHarvatek T4213 bit timing: a zero bit is 305 nanoseconds high then 945 low; a one bit is 610 high then 640 low; reset 200 microseconds low1 · Bit encoding, to scaleDINhighlowbit 0 period 1250 nsbit 1 period 1250 nsT0H 305 nsT1H 610 nsT0L 945 nsT1L 640 ns"0" bit"1" bit02505007501000125015001750200022502500time, ns2 · One frame: 24 bits, most-significant bit firstDIN170110010007100110101700101100bitch 1 · 8 bitsch 2 · 8 bitsch 3 · 8 bitsChannel order not recorded for this protocol · frame = 24 × ~1250 ns ≈ 30 µs · example data, first bits 1 0 1 …3 · RESET / latchlast bits of frame 1first bits of frame 2LEDs latch the data they receivedRESET: DIN low ≥ 200 µs (not to scale)4 · Cascade: each DOUT feeds the next DINMCULED 1DINDOUTLED 2DINDOUTLED NDINDOUTLED 1 keeps the first 24 bits, re-shapes the signal and sends the rest out on DOUT;LED 2 keeps the next 24, and so on. The last LED's DOUT is left unconnected.
T0H 305 / T0L 945 · T1H 610 / T1L 640 ns · period 1250 ns · reset 200 µs source: datasheet

Compatibility

  • electrically similar WS2812B

    Same 24-bit GRB frame and an 800 kHz bit rate, but the chip decides a bit by the length of its HIGH pulse alone (350 ns or less is a zero, 540 ns or more is a one) and tolerates bit periods up to 2.5 us. A WS2812B driver may work; the 200 us reset and the 50 us inter-byte limit are the traps. Not tested. source ↗

Dating evidence

Nobody announces these parts, so this records what we can actually cite rather than a release date. Library support proves only that the part existed by that date.

  • 2025-05-09 datasheet revision Harvatek T37G3GRB-12C0001X2U1930 datasheet (Preliminary) ↗ day

Similar parts

Same protocol or package first, then the same data scheme and colour channels.

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