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3.7 × 3.5 mm 4 pins top-emitting

SK6112MINI-RG

3735 · smd · SK6112 · OPSCO Optoelectronics

1-wire RGB 3.7–5.5 V active

Also sold as SK6112MINI-RG

At a glance

Colour
RGB8 bits per channel
Data
1-wiretimed pulses on one line
Supply
3.7–5.5 Vno backup data line
Size
3.7 × 3.5 × 1.1 mm4 pins · top
Max current
—per-channel not recorded
PWM
20 kHzreset 250 µs
Library support
FastLED WLED Adafruit

The SK6112 IC in the 3.5 x 3.7 x 1.1 mm mini package, with the SK6812MINI 3535 pin order (1 DIN, 2 VDD, 3 DOUT, 4 GND). T1H 0.65-1.0 us, reset above 250 us.

Variants

One row per orderable SKU. Everything not listed is inherited from the part above.

Order codeFaceLensWhite PinsSiliconStatusFirst seenDatasheet
SK6112MINI-RG — — — 4 — active 2019-02-16 A0
Stock 1,137 when checked.

Pinout

SK6112MINI-RG
SK6112MINI-RG 3735 package, top and side viewPin 1 is ringed. pin 1 DIN (data in), pin 2 VDD (power), pin 3 DOUT (data out), pin 4 GND (ground).11 DINdata in22 VDDpower33 DOUTdata out44 GNDground3.5 mm3.5 mmtop view1.1 mmside view
  • Data
  • Power
  • Ground
  • Pin 1
  • Cut corner

Outline and pin positions checked against the manufacturer datasheet (C5440781 sheet p4-5 (same drawing as SK6812MINI)). Pad widths taken from the SK6812MINI drawing. What this means.

  1. 1 DIN data in
  2. 2 VDD power
  3. 3 DOUT data out
  4. 4 GND ground

Protocol — SK6112

Timings shown from datasheet.

SK6112 bit timingSK6112 bit timing: a zero bit is 320 nanoseconds high then 900 low; a one bit is 900 high then 300 low; reset 250 microseconds low1 · Bit encoding, to scaleDINhighlowbit 0 period 1220 nsbit 1 period 1200 nsT0H 320 nsT1H 900 nsT0L 900 nsT1L 300 ns"0" bit"1" bit0250500750100012501500175020002250time, nsDatasheet lists unequal bit periods (1220 vs 1200 ns); each bit is drawn with its own.2 · One frame: 24 bits, most-significant bit firstDIN170110010007100110101700101100bitch 1 · 8 bitsch 2 · 8 bitsch 3 · 8 bitsChannel order not recorded for this protocol · frame = 24 × ~1220 ns ≈ 29.3 µs · example data, first bits 1 0 1 …3 · RESET / latchlast bits of frame 1first bits of frame 2LEDs latch the data they receivedRESET: DIN low ≥ 250 µs (not to scale)4 · Cascade: each DOUT feeds the next DINMCULED 1DINDOUTLED 2DINDOUTLED NDINDOUTLED 1 keeps the first 24 bits, re-shapes the signal and sends the rest out on DOUT;LED 2 keeps the next 24, and so on. The last LED's DOUT is left unconnected.
T0H 320 / T0L 900 · T1H 900 / T1L 300 ns · reset 250 µs source: datasheet

Compatibility

  • protocol compatible SK6812

    Accepts SK6812-style 24-bit frames in its default mode and sits in the same 5050 and 3.5 x 3.7 mm packages with the same pad positions, but it is a different IC with extra commands (feedback, current gain, sleep, IDs) and a 250 us reset. Whether a plain SK6812 driver is fully compatible has not been tested. source ↗

  • electrically similar of this TONYU 6112

    Inferred from the part code, the described feature set and the printed numbers; the TONYU sheet never names OPSCO or SK6112. OPSCO's SK6112-RG-002 sheet prints T0H 250/320/400, T0L at least 800, T1H 750/900/1000, T1L at least 200 ns and reset above 250 us, and (per this catalogue's SK6112 entry) has a command mode with feedback and current gain; TONYU's windows are slightly wider (T0H 150-450, T1H 750-1050) and its PWM is 1.2 kHz where OPSCO's advanced mode defaults to 20 kHz. The command protocol is not printed in the TONYU sheet, so command-level compatibility is unknown.

Dating evidence

Nobody announces these parts, so this records what we can actually cite rather than a release date. Library support proves only that the part existed by that date.

  • 2019-02-16 datasheet revision OPSCO SK6112MINI-RG datasheet revision table: 01 first issue ↗ day
  • 2019-02-16 datasheet revision OPSCO SK6112-RG datasheet (LCSC C5440833) revision table: 'A/0 2019-02-16 first issue' ↗ day

Where to buy

Stub data — a few rows so purchase links can grow later. Prices are not tracked.

Similar parts

Same protocol or package first, then the same data scheme and colour channels.

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