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SK6112

1-wire RGB · OPSCO Optoelectronics · sk68xx

Channels
RGB
Bits / channel
8
Supply
3.7–5.5 V
PWM
20 kHz
Backup data
no
Packages
2

A second-generation OPSCO driver (“Gen 2” in its own datasheet): backward link feedback, 32-step current gain, adjustable PWM, a 5 uA sleep mode, parallel channels and dynamic or fixed addressing. Seeded from two LCSC datasheets; the command set is not modelled.

Refresh & flicker

PWM is adjustable from 1.2 to 20 kHz, default 20 kHz, per the sheet’s “Gen 2” advanced mode - far above the SK6812’s 1.0-1.2 kHz.

Timing

SK6112 bit timingSK6112 bit timing: a zero bit is 320 nanoseconds high then 900 low; a one bit is 900 high then 300 low; reset 250 microseconds low1 · Bit encoding, to scaleDINhighlowbit 0 period 1220 nsbit 1 period 1200 nsT0H 320 nsT1H 900 nsT0L 900 nsT1L 300 ns"0" bit"1" bit0250500750100012501500175020002250time, nsDatasheet lists unequal bit periods (1220 vs 1200 ns); each bit is drawn with its own.2 · One frame: 24 bits, most-significant bit firstDIN170110010007100110101700101100bitch 1 · 8 bitsch 2 · 8 bitsch 3 · 8 bitsChannel order not recorded for this protocol · frame = 24 × ~1220 ns ≈ 29.3 µs · example data, first bits 1 0 1 …3 · RESET / latchlast bits of frame 1first bits of frame 2LEDs latch the data they receivedRESET: DIN low ≥ 250 µs (not to scale)4 · Cascade: each DOUT feeds the next DINMCULED 1DINDOUTLED 2DINDOUTLED NDINDOUTLED 1 keeps the first 24 bits, re-shapes the signal and sends the rest out on DOUT;LED 2 keeps the next 24, and so on. The last LED's DOUT is left unconnected.
T0H 320 / T0L 900 · T1H 900 / T1L 300 ns · reset 250 µs source: datasheet
SourceT0HT0LT1HT1LPeriodRateReset±
datasheet ↗ 320 ns 900 ns 900 ns 300 ns 1220 ns 820 kHz 250 µs —
A min/typ/max table: T0H 250/320/400 ns, T0L 800/900 ns (no maximum), T1H 750/900/1000 ns, T1L 200/300 ns (no maximum); reset above 250 us. The sheet’s later sections describe a command protocol built on the reset timing (“reset command set”), which this catalogue has not transcribed.

Clones & compatibility

“Compatible” is never stated bare here — each relationship carries how strong the claim is, and what bites if you assume too much.

  • protocol compatible SK6812

    Accepts SK6812-style 24-bit frames in its default mode and sits in the same 5050 and 3.5 x 3.7 mm packages with the same pad positions, but it is a different IC with extra commands (feedback, current gain, sleep, IDs) and a 250 us reset. Whether a plain SK6812 driver is fully compatible has not been tested. source ↗

  • electrically similar of this TONYU 6112

    Inferred from the part code, the described feature set and the printed numbers; the TONYU sheet never names OPSCO or SK6112. OPSCO's SK6112-RG-002 sheet prints T0H 250/320/400, T0L at least 800, T1H 750/900/1000, T1L at least 200 ns and reset above 250 us, and (per this catalogue's SK6112 entry) has a command mode with feedback and current gain; TONYU's windows are slightly wider (T0H 150-450, T1H 750-1050) and its PWM is 1.2 kHz where OPSCO's advanced mode defaults to 20 kHz. The command protocol is not printed in the TONYU sheet, so command-level compatibility is unknown.

Library support

Not checked against library source.

Parts using this protocol

Dating evidence

Evidence, not a release date. A library commit proves the part existed by that date and says nothing about how long before.

  • 2019-02-16 datasheet revision OPSCO SK6112-RG datasheet (LCSC C5440833) revision table: 'A/0 2019-02-16 first issue' ↗ day