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TONYU 6112

1-wire RGB · TONYU · tonyu

Channels
RGB
Bits / channel
8
Supply
3.5–5.5 V
PWM
1.2 kHz
Backup data
no
Packages
1

TONYU’s single-wire IC with a two-way mode, “6112” in the part number, in the 4.0 x 1.6 x 2.0 mm side-view package. Its overview calls the IC a “single-wire two-way communication constant-current driver” with data regeneration.

Datasheets disagree with themselves: the feature list says the control circuit is integrated “in a 5050 package” (copied from the 5050 sheet) while the drawing shows a 4.0 x 1.6 x 2.0 mm body.

Refresh & flicker

PWM 1.2 kHz, quiescent 2 mA, internal supply 5.2 V typical, thresholds 0.7 / 0.3 x VDD (page 8); data rate 800 kbps, DIN to DOUT delay at most 300 ns (CL = 15 pF, 10 kohm), output rise/fall at most 200 ns (page 4).

Timing

TONYU 6112 bit timingTONYU 6112 bit timing: a zero bit is 300 nanoseconds high then 750 low; a one bit is 900 high then 150 low; reset 250 microseconds low1 · Bit encoding, to scaleDINhighlowbit 0 period 1050 nsbit 1 period 1050 nsT0H 300 nsT1H 900 nsT0L 750 nsT1L 150 ns"0" bit"1" bit0200400600800100012001400160018002000time, ns2 · One frame: 24 bits, most-significant bit firstDIN170110010007100110101700101100bitch 1 · 8 bitsch 2 · 8 bitsch 3 · 8 bitsChannel order not recorded for this protocol · frame = 24 × ~1050 ns ≈ 25.2 µs · example data, first bits 1 0 1 …3 · RESET / latchlast bits of frame 1first bits of frame 2LEDs latch the data they receivedRESET: DIN low ≥ 250 µs (not to scale)4 · Cascade: each DOUT feeds the next DINMCULED 1DINDOUTLED 2DINDOUTLED NDINDOUTLED 1 keeps the first 24 bits, re-shapes the signal and sends the rest out on DOUT;LED 2 keeps the next 24, and so on. The last LED's DOUT is left unconnected.
T0H 300 / T0L 750 · T1H 900 / T1L 150 ns · period 1050 ns · reset 250 µs source: datasheet
SourceT0HT0LT1HT1LPeriodRateReset±
datasheet ↗ 300 ns 750 ns 900 ns 150 ns 1200 ns 833 kHz 250 µs —
Min/typ/max table: T0H 150/300/450 ns, T0L 750 ns minimum (no typical), T1H 750/900/1050 ns, T1L 150 ns minimum (no typical), symbol period 1.2 us minimum, reset above 250 us; T0L and T1L are minimums, not nominals. Low time of a 0 or 1 code under 20 us. 24 bits G, R, B high bit first (page 6). The sheet also describes a “high-order working mode” entered by a command sequence: bidirectional transmission that reports the pixel count and current configuration back to the controller, and 5-bit (32-step) current gain per colour. The command encoding is not printed and is not transcribed here.

Clones & compatibility

“Compatible” is never stated bare here — each relationship carries how strong the claim is, and what bites if you assume too much.

  • electrically similar SK6112

    Inferred from the part code, the described feature set and the printed numbers; the TONYU sheet never names OPSCO or SK6112. OPSCO's SK6112-RG-002 sheet prints T0H 250/320/400, T0L at least 800, T1H 750/900/1000, T1L at least 200 ns and reset above 250 us, and (per this catalogue's SK6112 entry) has a command mode with feedback and current gain; TONYU's windows are slightly wider (T0H 150-450, T1H 750-1050) and its PWM is 1.2 kHz where OPSCO's advanced mode defaults to 20 kHz. The command protocol is not printed in the TONYU sheet, so command-level compatibility is unknown. source ↗

Library support

Not checked against library source.

Parts using this protocol

Dating evidence

Evidence, not a release date. A library commit proves the part existed by that date and says nothing about how long before.

  • 2019 first documented TONYU DY-S204016/RGBC/6112-1.5T specification, footer 'Copyright 2019, TONYU' (no issue date printed; version A1.0) ↗ year