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Meihua MHP5050 IC (unnamed)

1-wire RGB · MEIHUA · meihua

Channels
RGB
Bits / channel
8
Supply
3–7.5 V
PWM
—
Backup data
no
Packages
1

The driver inside Meihua’s 5050 “IC RGB” PLCC. The sheet gives GRB colour order and 295/595 ns timing, unlike the same maker’s MHP1515 sheet (RGB order, 300/900 ns, reset above 200 us); the two are separate protocols.

Refresh & flicker

PWM is listed as “3~5 kHz” in the parameter-limitation table (page 5), a range rather than a typical, so the field is left empty. Data rate 800 typical / 1100 kHz maximum, DIN to DOUT delay at most 200 ns (CL = 30 pF), rise and fall at most 400 ns (page 7). Sleep current 0.6 / 0.8 / 1 mA, input thresholds 0.7 and 0.3 x VDD, per-colour sink current 12 mA minimum / 15 mA maximum with VDD - Vf at least 1.2 V (page 6); absolute maximum output current 15 mA, power 400 mW.

Timing

Meihua MHP5050 IC (unnamed) bit timingMeihua MHP5050 IC (unnamed) bit timing: a zero bit is 295 nanoseconds high then 595 low; a one bit is 595 high then 295 low; tolerance plus or minus 50 nanoseconds; reset 80 microseconds low1 · Bit encoding, to scaleDINhighlowbit 0 period 890 nsbit 1 period 890 nsT0H 295 ±50 nsT1H 595 ±50 nsT0L 595 ±50 nsT1L 295 ±50 ns"0" bit"1" bit02004006008001000120014001600time, ns± tolerance on each falling edge2 · One frame: 24 bits, most-significant bit firstDIN170110010007100110101700101100bitch 1 · 8 bitsch 2 · 8 bitsch 3 · 8 bitsChannel order not recorded for this protocol · frame = 24 × ~890 ns ≈ 21.4 µs · example data, first bits 1 0 1 …3 · RESET / latchlast bits of frame 1first bits of frame 2LEDs latch the data they receivedRESET: DIN low ≥ 80 µs (not to scale)4 · Cascade: each DOUT feeds the next DINMCULED 1DINDOUTLED 2DINDOUTLED NDINDOUTLED 1 keeps the first 24 bits, re-shapes the signal and sends the rest out on DOUT;LED 2 keeps the next 24, and so on. The last LED's DOUT is left unconnected.
T0H 295 / T0L 595 · T1H 595 / T1L 295 ns · ±50 ns · period 890 ns · reset 80 µs source: datasheet
SourceT0HT0LT1HT1LPeriodRateReset±
datasheet ↗ 295 ns 595 ns 595 ns 295 ns 890 ns 1124 kHz 80 µs 50 ns
Printed as a single “Typ.” column with a +/-0.05 us tolerance: T0H 0.295, T1H 0.595, T0L 0.595, T1L 0.295 us, reset at least 80 us (the table’s Min and Max columns are empty). Data is 24 bits, high bytes first, in G, R, B order (page 8).

Clones & compatibility

“Compatible” is never stated bare here — each relationship carries how strong the claim is, and what bites if you assume too much.

  • electrically similar Amicc SC5050A-B02

    The Amicc A-SC5050ARGBC-B02 sheet (Feb 2023) prints the same parameter limitation, electrical, dynamic and timing tables as the Meihua sheet (June 2022) number for number, and the same 5.4 x 5.0 mm outline and pin order; neither sheet names the IC or says it is a second source. The two are kept separate because the sheets are by different companies. source ↗

  • electrically similar TZ2812

    The TUOZHAN TZ2812 sheet prints the same typical timing figures (T0H 295 / T0L 595 / T1H 595 / T1L 295 ns), 80 us reset and GRB order, and the same 5050 pin order. Window widths differ (TZ2812: T0H 200-350 ns; Meihua: 295 +/-50 ns), supply is 3.0-7.5 versus 3.5-7.5 V, and PWM is 3-5 kHz versus 4 kHz. No sheet states that one is a copy of the other. source ↗

  • electrically similar of this Amicc SC5050A-B02

    Identical tables to the Meihua MHP5050 sheet (see that protocol); neither sheet names the IC.

Library support

Not checked against library source.

Parts using this protocol

Dating evidence

Evidence, not a release date. A library commit proves the part existed by that date and says nothing about how long before.

  • 2022-06-10 datasheet revision Meihua MHP5050ICRGBCT data sheet Rev.1, date on the cover (Issue No LPDS-0030217) ↗ day