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TX1812CXU

1-wire RGB · TCWIN · tx18xx

Channels
RGB
Bits / channel
8
Supply
3.5–5.5 V
PWM
4.5 kHz
Backup data
no
Packages
1

The 2024 TX1812 5050 sheet that differs from every 2023 TX1812 sheet: 11.5 mA drive, absolute thresholds (input high at least 3.1 V, low at most 1.5 V) rather than fractions of VDD, 10 V output-port rating, DO source/sink ±14 mA, 2 kV ESD (the others 4 kV), 0.45 mA static current, PWM 4.5 kHz and a 200 us reset. Only one package (5050) and one SKU on LCSC. Whether the U in the part number is what marks this version is not stated by any sheet.

Refresh & flicker

Data rate 800 kHz typical, 4.5 kHz PWM, 0.45 mA static, propagation delay 80 ns typical, rise/fall 500 ns, GRB order. Output port rating 10 V, DO ±14 mA.

Timing

TX1812CXU bit timingTX1812CXU bit timing: a zero bit is 300 nanoseconds high then 900 low; a one bit is 900 high then 300 low; tolerance plus or minus 50 nanoseconds; reset 200 microseconds low1 · Bit encoding, to scaleDINhighlowbit 0 period 1200 nsbit 1 period 1200 nsT0H 300 ±50 nsT1H 900 ±50 nsT0L 900 ±50 nsT1L 300 ±50 ns"0" bit"1" bit020040060080010001200140016001800200022002400time, ns± tolerance on each falling edge2 · One frame: 24 bits, most-significant bit firstDIN170110010007100110101700101100bitch 1 · 8 bitsch 2 · 8 bitsch 3 · 8 bitsChannel order not recorded for this protocol · frame = 24 × ~1200 ns ≈ 28.8 µs · example data, first bits 1 0 1 …3 · RESET / latchlast bits of frame 1first bits of frame 2LEDs latch the data they receivedRESET: DIN low ≥ 200 µs (not to scale)4 · Cascade: each DOUT feeds the next DINMCULED 1DINDOUTLED 2DINDOUTLED NDINDOUTLED 1 keeps the first 24 bits, re-shapes the signal and sends the rest out on DOUT;LED 2 keeps the next 24, and so on. The last LED's DOUT is left unconnected.
T0H 300 / T0L 900 · T1H 900 / T1L 300 ns · ±50 ns · period 1200 ns · reset 200 µs source: datasheet
SourceT0HT0LT1HT1LPeriodRateReset±
datasheet ↗ 300 ns 900 ns 900 ns 300 ns 1200 ns 833 kHz 200 µs 50 ns
Typical values with a symmetric ±0.05 us tolerance: T0H 0.3 us, T0L 0.9 us, T1H 0.9 us, T1L 0.3 us, reset at least 200 us.

Clones & compatibility

“Compatible” is never stated bare here — each relationship carries how strong the claim is, and what bites if you assume too much.

  • protocol compatible SK6805

    The typical timing (300 / 900 / 900 / 300 ns, 200 us reset) equals the OPSCO SK6805-EC15 sheet figures recorded on the sk6805 protocol, with the same 24-bit GRB framing. The numbers coincide; neither sheet claims compatibility, the drive current is 11.5 mA here against 5 mA, and the +-50 ns tolerance is narrower than the SK6805 windows. Not measured. source ↗

Library support

Not checked against FastLED’s chipset list or the other libraries’ source.

Parts using this protocol

Dating evidence

Evidence, not a release date. A library commit proves the part existed by that date and says nothing about how long before.

  • 2024-07-18 datasheet revision TCWIN TX1812CXU-F01 specification cover: date 20240718, version A5 ↗ day