5.4 × 5.0 mm 4 pins top-emitting

A-SC5050ARGBC-B02-03-1T

5050 · smd · Amicc SC5050A-B02 · Amicc

1-wire RGB 3–7.5 V active

Also sold as A-SC5050ARGBC-B02-03-1T, Amicc 5050

At a glance

Colour
RGB8 bits per channel
Data
1-wiretimed pulses on one line
Supply
3–7.5 Vno backup data line
Size
5.4 × 5.0 × 1.6 mm4 pins · top
Max current
—12 mA per channel
PWM
—reset 80 µs
Library support
FastLED WLED Adafruit

Amicc’s four-pad 5050 pixel: the same 5.4 x 5.0 mm outline, pads and pin order as the WS2812B-5050 (1 VDD, 2 DOUT, 3 VSS, 4 DIN, cut corner at pin 3). The sheet does carry a data input: DIN is a real pin, with DOUT passing the data on. The sheet’s tables are the same as the Meihua MHP5050 sheet’s; see the protocol page. LCSC stock 1,740.

Variants

One row per orderable SKU. Everything not listed is inherited from the part above.

Order codeFaceLensWhite PinsSiliconStatusFirst seenDatasheet
A-SC5050ARGBC-B02-03-1T — — — 4 — active 2023-02-01 v2
LCSC stock 1,740 on 2026-10-15.

Pinout

A-SC5050ARGBC-B02-03-1T
A-SC5050ARGBC-B02-03-1T 5050 package, top and side viewPin 1 is ringed. pin 1 VDD (power), pin 2 DOUT (data out), pin 3 VSS (ground), pin 4 DIN (data in).11 VDDpower22 DOUTdata out33 VSSground44 DINdata in5.4 mm overall5.0 mmtop view1.6 mmside view
  • Power
  • Data
  • Ground
  • Pin 1
  • Cut corner

Outline and pin positions checked against the manufacturer datasheet (C7433063 A-SC5050ARGBC-B02-03-1T v2, p3 (package dimensions, pin table)). Numbered counter-clockwise from the top-left; the cut corner is at pin 3 (VSS). What this means.

  1. 1 VDD power
  2. 2 DOUT data out
  3. 3 VSS ground
  4. 4 DIN data in

Protocol — Amicc SC5050A-B02

Timings shown from datasheet.

Amicc SC5050A-B02 bit timingAmicc SC5050A-B02 bit timing: a zero bit is 295 nanoseconds high then 595 low; a one bit is 595 high then 295 low; tolerance plus or minus 50 nanoseconds; reset 80 microseconds low1 · Bit encoding, to scaleDINhighlowbit 0 period 890 nsbit 1 period 890 nsT0H 295 ±50 nsT1H 595 ±50 nsT0L 595 ±50 nsT1L 295 ±50 ns"0" bit"1" bit02004006008001000120014001600time, ns± tolerance on each falling edge2 · One frame: 24 bits, most-significant bit firstDIN170110010007100110101700101100bitch 1 · 8 bitsch 2 · 8 bitsch 3 · 8 bitsChannel order not recorded for this protocol · frame = 24 × ~890 ns ≈ 21.4 µs · example data, first bits 1 0 1 …3 · RESET / latchlast bits of frame 1first bits of frame 2LEDs latch the data they receivedRESET: DIN low ≥ 80 µs (not to scale)4 · Cascade: each DOUT feeds the next DINMCULED 1DINDOUTLED 2DINDOUTLED NDINDOUTLED 1 keeps the first 24 bits, re-shapes the signal and sends the rest out on DOUT;LED 2 keeps the next 24, and so on. The last LED's DOUT is left unconnected.
T0H 295 / T0L 595 · T1H 595 / T1L 295 ns · ±50 ns · period 890 ns · reset 80 µs source: datasheet

Compatibility

Dating evidence

Nobody announces these parts, so this records what we can actually cite rather than a release date. Library support proves only that the part existed by that date.

  • 2023-02-01 datasheet revision Amicc A-SC5050ARGBC-B02-03-1T datasheet, 'Release Date: 01.Feb.2023, Issue No: v2' (ADE-5050A-002) ↗ day

Where to buy

Stub data — a few rows so purchase links can grow later. Prices are not tracked.

Similar parts

Same protocol or package first, then the same data scheme and colour channels.

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