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3.5 × 2.8 mm 4 pins top-emitting

T68

3528 · smd · TCWIN T63 group · TCWIN

1-wire RGB 3.5–5.5 V active

At a glance

Colour
RGB8 bits per channel
Data
1-wiretimed pulses on one line
Supply
3.5–5.5 Vno backup data line
Size
3.5 × 2.8 × 1.8 mm4 pins · top
Max current
36 mA12 mA per channel
PWM
4 kHzreset 80 µs
Library support
FastLED WLED Adafruit

TCWIN T68: a 3.5 x 2.8 x 1.75 mm built-in-IC LED, 12 mA per channel (9.6-14.4), cover rating 0.18 W, version A5 dated 2024-07-18. Same drawing and pins as T67 (1 VDD, 2 DO, 3 GND, 4 DIN).

Variants

One row per orderable SKU. Everything not listed is inherited from the part above.

Order codeFaceLensWhite PinsSiliconStatusFirst seenDatasheet
T68 — — — 4 — active 2024-07-18 A5
LCSC stock 1,980 on 2026-10-15.

Pinout

T68
T68 3528 package, top and side viewPin 1 is ringed. pin 1 VDD (power), pin 2 DO (data out), pin 3 GND (ground), pin 4 DIN (data in).11 VDDpower22 DOdata out33 GNDground44 DINdata in3.5 mm overall2.8 mmtop view1.8 mmside view
  • Power
  • Data
  • Ground
  • Pin 1
  • Cut corner

Outline and pin positions checked against the manufacturer datasheet (C48982521 T68 rev A5 p4). Body 3.2 wide, 3.5 across the leads. Lead length and pitch read from the back view; the lead height (0.65 mm) is the land-pattern height and approximate. What this means.

  1. 1 VDD power
  2. 2 DO data out
  3. 3 GND ground
  4. 4 DIN data in

Protocol — TCWIN T63 group

Timings shown from datasheet.

TCWIN T63 group bit timingTCWIN T63 group bit timing: a zero bit is 300 nanoseconds high then 600 low; a one bit is 600 high then 300 low; reset 80 microseconds low1 · Bit encoding, to scaleDINhighlowbit 0 period 900 nsbit 1 period 900 nsT0H 300 nsT1H 600 nsT0L 600 nsT1L 300 ns"0" bit"1" bit020040060080010001200140016001800time, ns2 · One frame: 24 bits, most-significant bit firstDIN170110010007100110101700101100bitch 1 · 8 bitsch 2 · 8 bitsch 3 · 8 bitsChannel order not recorded for this protocol · frame = 24 × ~900 ns ≈ 21.6 µs · example data, first bits 1 0 1 …3 · RESET / latchlast bits of frame 1first bits of frame 2LEDs latch the data they receivedRESET: DIN low ≥ 80 µs (not to scale)4 · Cascade: each DOUT feeds the next DINMCULED 1DINDOUTLED 2DINDOUTLED NDINDOUTLED 1 keeps the first 24 bits, re-shapes the signal and sends the rest out on DOUT;LED 2 keeps the next 24, and so on. The last LED's DOUT is left unconnected.
T0H 300 / T0L 600 · T1H 600 / T1L 300 ns · period 900 ns · reset 80 µs source: datasheet

Compatibility

  • protocol compatible TX1812

    The TX1812 sheets print T0H 245-345 and T0L 545-645 ns; the typical 295 / 595 ns pair lies inside the T63 windows (220-400 / 550-950 ns) and the T63 typicals (300 / 600 ns) lie inside the TX1812 windows, so one stream satisfies both printed sets. Supply, GRB framing and the other electrical tables are the same. Numbers only; no sheet relates the two, and nothing was measured. source ↗

Dating evidence

Nobody announces these parts, so this records what we can actually cite rather than a release date. Library support proves only that the part existed by that date.

  • 2024-07-18 datasheet revision TCWIN T68 specification cover: date 20240718, version A5 ↗ day
  • 2024-07-18 datasheet revision TCWIN T63 / T66 / T67 / T68 / T71 / T73 / T76 specification covers: date 20240718, version A5 ↗ day

Where to buy

Stub data — a few rows so purchase links can grow later. Prices are not tracked.

Similar parts

Same protocol or package first, then the same data scheme and colour channels.

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