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4.0 × 1.7 mm 4 pins emission unknown-emitting

T73

4018 · smd · TCWIN T63 group · TCWIN

1-wire RGB 3.5–5.5 V active

At a glance

Colour
RGB8 bits per channel
Data
1-wiretimed pulses on one line
Supply
3.5–5.5 Vno backup data line
Size
4.0 × 1.7 × 2.0 mm4 pins · emission unknown
Max current
15 mA5 mA per channel
PWM
4 kHzreset 80 µs
Library support
FastLED WLED Adafruit

TCWIN T73: the 5 mA version of the T71 package: 4.0 x 1.7 x 2.0 mm four-pad row (1 DIN, 2 VDD, 3 DO, 4 GND), cover rating 0.08 W, version A5 dated 2024-07-18, same drawing as T71.

Variants

One row per orderable SKU. Everything not listed is inherited from the part above.

Order codeFaceLensWhite PinsSiliconStatusFirst seenDatasheet
T73 — — — 4 — active 2024-07-18 A5
LCSC stock 1,220 on 2026-10-15.

Pinout

T73
T73 4018 package, top and side viewPin 1 is ringed. pin 1 DIN (data in), pin 2 VDD (power), pin 3 DO (data out), pin 4 GND (ground).11 DIN22 VDD33 DO44 GND4.0 mm1.7 mmfront view (lens face)2.0 mm deepside view
  • Data
  • Power
  • Ground
  • Pin 1

Outline and pin positions checked against the manufacturer datasheet (C48982526 T73 rev A5 p4). Four pads in a row, numbered left to right in the sheet front view (1 DIN, 2 VDD, 3 DO, 4 GND). The sheet does not use the words side view; pad height approximate (land pattern 1.2 mm tall). What this means.

  1. 1 DIN data in
  2. 2 VDD power
  3. 3 DO data out
  4. 4 GND ground

Protocol — TCWIN T63 group

Timings shown from datasheet.

TCWIN T63 group bit timingTCWIN T63 group bit timing: a zero bit is 300 nanoseconds high then 600 low; a one bit is 600 high then 300 low; reset 80 microseconds low1 · Bit encoding, to scaleDINhighlowbit 0 period 900 nsbit 1 period 900 nsT0H 300 nsT1H 600 nsT0L 600 nsT1L 300 ns"0" bit"1" bit020040060080010001200140016001800time, ns2 · One frame: 24 bits, most-significant bit firstDIN170110010007100110101700101100bitch 1 · 8 bitsch 2 · 8 bitsch 3 · 8 bitsChannel order not recorded for this protocol · frame = 24 × ~900 ns ≈ 21.6 µs · example data, first bits 1 0 1 …3 · RESET / latchlast bits of frame 1first bits of frame 2LEDs latch the data they receivedRESET: DIN low ≥ 80 µs (not to scale)4 · Cascade: each DOUT feeds the next DINMCULED 1DINDOUTLED 2DINDOUTLED NDINDOUTLED 1 keeps the first 24 bits, re-shapes the signal and sends the rest out on DOUT;LED 2 keeps the next 24, and so on. The last LED's DOUT is left unconnected.
T0H 300 / T0L 600 · T1H 600 / T1L 300 ns · period 900 ns · reset 80 µs source: datasheet

Compatibility

  • protocol compatible TX1812

    The TX1812 sheets print T0H 245-345 and T0L 545-645 ns; the typical 295 / 595 ns pair lies inside the T63 windows (220-400 / 550-950 ns) and the T63 typicals (300 / 600 ns) lie inside the TX1812 windows, so one stream satisfies both printed sets. Supply, GRB framing and the other electrical tables are the same. Numbers only; no sheet relates the two, and nothing was measured. source ↗

Dating evidence

Nobody announces these parts, so this records what we can actually cite rather than a release date. Library support proves only that the part existed by that date.

  • 2024-07-18 datasheet revision TCWIN T73 specification cover: date 20240718, version A5 ↗ day
  • 2024-07-18 datasheet revision TCWIN T63 / T66 / T67 / T68 / T71 / T73 / T76 specification covers: date 20240718, version A5 ↗ day

Where to buy

Stub data — a few rows so purchase links can grow later. Prices are not tracked.

Similar parts

Same protocol or package first, then the same data scheme and colour channels.

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