Everlight 3-channel 8-bit PWM single-wire IC

1-wire RGB · Everlight Electronics · everlight

Channels
RGB
Bits / channel
8
Supply
4.5–5.5 V
PWM
—
Backup data
no
Packages
5

The sheets name no IC; the cell is called ‘3-channels LED driver with 8 bit PWM linear control’ (19-C47, 12-23C, 4516-IC, 61-236-IC). The same electrical tables (DIN to DOUT delay, fall time, input capacitance, 0.35 V hysteresis, ‘DIN / SET’ thresholds) reappear word for word in the Lite-On LTST sheets and the Lumex SMD-LX0707RGB-TR sheet; the Lumex part also reuses the 12-23C timing and 5 V application figure. That suggests one IC supplied to several LED makers, but no sheet says so. Lumex’s sheet is reused on this protocol; Lite-On’s variants live in liteon-ic.

Refresh & flicker

800 kbps (‘Clock frequency 800 kbps’ in the absolute maximum table), 8 bit PWM per channel (256 grey levels), 24 bit per pixel sent R first, then G, then B, MSB first (figure ‘Single Data in 24bit for RGB’: OUTR[7]…OUTR[0], OUTG[7]…, OUTB[7]…). The 12-23C / 19-C47 sheets give a DIN to DOUT delay of 300 ns max (CL 15 pF, RL 10 k) and a 20 us falling time on the output with 300 pF; the 4516 and 61-236 sheets list a 0.35 V hysteresis and a DIN / SET input. Supply: abs max 3.8-5.5 V (12-23C), 4.2-5.5 V (19-C47, 61-236) and 6.5 V (4516); recommended 5 V typical. The sheets print no PWM frequency.

Timing

Sources disagree. This is normal and worth understanding: FastLED's numbers are tuned to drive real parts reliably, including clones, while the datasheet gives the manufacturer's nominal figures. Both are recorded here rather than picking one and hiding the conflict.

Everlight 3-channel 8-bit PWM single-wire IC bit timingEverlight 3-channel 8-bit PWM single-wire IC bit timing: a zero bit is 300 nanoseconds high then 900 low; a one bit is 900 high then 300 low; tolerance plus or minus 80 nanoseconds; reset 50 microseconds low1 · Bit encoding, to scaleDINhighlowbit 0 period 1200 nsbit 1 period 1200 nsT0H 300 ±80 nsT1H 900 ±80 nsT0L 900 ±80 nsT1L 300 ±80 ns"0" bit"1" bit020040060080010001200140016001800200022002400time, ns± tolerance on each falling edge2 · One frame: 24 bits, most-significant bit firstDIN170110010007100110101700101100bitch 1 · 8 bitsch 2 · 8 bitsch 3 · 8 bitsChannel order not recorded for this protocol · frame = 24 × ~1200 ns ≈ 28.8 µs · example data, first bits 1 0 1 …3 · RESET / latchlast bits of frame 1first bits of frame 2LEDs latch the data they receivedRESET: DIN low ≥ 50 µs (not to scale)4 · Cascade: each DOUT feeds the next DINMCULED 1DINDOUTLED 2DINDOUTLED NDINDOUTLED 1 keeps the first 24 bits, re-shapes the signal and sends the rest out on DOUT;LED 2 keeps the next 24, and so on. The last LED's DOUT is left unconnected.
T0H 300 / T0L 900 · T1H 900 / T1L 300 ns · ±80 ns · period 1200 ns · reset 50 µs source: datasheet
SourceT0HT0LT1HT1LPeriodRateReset±
datasheet ↗ 300 ns 900 ns 900 ns 300 ns 1200 ns 833 kHz 50 µs 80 ns
T0H 300 ns +/-80, T0L 900 ns +/-80, T1H 900 ns +/-80, T1L 300 ns +/-80, reset >50 us. The cascade figure adds ‘>1.2 us ~ <3.6 us’ between 24-bit words.
datasheet ↗ 300 ns 900 ns 900 ns 300 ns 1200 ns 833 kHz 250 µs 150 ns
Same typicals with +/-0.15 us. The reset row of this sheet reads ‘RES: low voltage time above 250 us’ while the waveform below it and the description (p1, ‘reset signal (>50us low-level signal)’) say ‘Latch time >50 us’.

Clones & compatibility

“Compatible” is never stated bare here — each relationship carries how strong the claim is, and what bites if you assume too much.

Library support

Not checked against FastLED, Adafruit or WLED source.

Parts using this protocol

Dating evidence

Evidence, not a release date. A library commit proves the part existed by that date and says nothing about how long before.

  • 2019-10-24 datasheet revision Everlight 19-C47/RSGHBHC-5V01/2T data sheet, footer 'Release Date : 24-Oct-2019, Rev.5' ↗ day