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2.0 × 1.8 mm 4 pins top-emitting

CT-2018

2018 · smd · Chongtian M2 / M3 single-wire IC (0.3 / 0.9 us) · Chongtian

1-wire RGB 3.5–5.5 V active

Also sold as 0807 RGB, CT-2018URGBC

At a glance

Colour
RGB8 bits per channel
Data
1-wiretimed pulses on one line
Supply
3.5–5.5 Vno backup data line
Size
2.0 × 1.8 × 0.8 mm4 pins · top
Max current
36 mA12 mA per channel
PWM
4.5 kHzreset 200 µs
Library support
FastLED WLED Adafruit

2.0 x 1.8 x 0.8 mm (‘0807’). Six SKUs on three IC cells, listed as variants: M3 (5 mA), M2 (12 mA) and MX3 (12 mA, other timing). Datasheets disagree: the CT-2018URGBC/H-P8 sheet’s text says the reset is 80 us while its table says >200 us; its 24-bit figure prints R, G, B rows under a note saying GRB; its overview paragraph and feature list talk about a ‘W LED chip’ although it is an RGB part; and the ‘SURGBC’ and ‘HW’ cover names carry ‘RGB-M2’ where the 2026 sheets say ‘GRB’. The two flash types in the same package, CT-2018URGBC/K-P8-H10 (C56145018) and /M-P8-H11 (C56145019), are two-pin self-flashing LEDs (VSS / VDD only) and are skipped. LCSC stock: C52191326 2,460, C52191327 0, C52191328 980, C52191329 960, C56145017 3,000, C56145023 2,980.

Variants

One row per orderable SKU. Everything not listed is inherited from the part above.

Order codeFaceLensWhite PinsSiliconStatusFirst seenDatasheet
CT-2018URGBC/H-P8 — clear — 4 — active 2023-01-05 A2A1 ↗A1 ↗A1 ↗A1 ↗A2 ↗
LCSC C52191326, stock 2,460. M3 cell, 5 mA.
CT-2018SURGBC/H-P8 — clear — 4 — active 2023-01-05 A2A1 ↗A1 ↗A1 ↗A1 ↗A2 ↗
LCSC C52191328, stock 980. M2 cell, 12 mA.
CT-2018URGBC/HW-P8 — frosted — 4 — active 2023-01-05 A2A1 ↗A1 ↗A1 ↗A1 ↗A2 ↗
LCSC C52191329, stock 960. M2 cell, 12 mA, frosted.
CT-2018URGBC/H-P8-MX3 — clear — 4 — active 2023-01-05 A2A1 ↗A1 ↗A1 ↗A1 ↗A2 ↗
LCSC C52191327, stock 0. MX3 cell, 12 mA.
CT-2018UGRBC/HW-P8-M2 — frosted — 4 — active 2023-01-05 A2A1 ↗A1 ↗A1 ↗A1 ↗A2 ↗
LCSC C56145017, stock 3,000. M2 cell, 12 mA, frosted; 2026 sheet.
CT-2018UGRBC/H-P8-M2 — clear — 4 — active 2023-01-05 A2A1 ↗A1 ↗A1 ↗A1 ↗A2 ↗
LCSC C56145023, stock 2,980. M2 cell, 12 mA; 2026 sheet.

Pinout

CT-2018URGBC/H-P8CT-2018SURGBC/H-P8CT-2018URGBC/HW-P8CT-2018URGBC/H-P8-MX3CT-2018UGRBC/HW-P8-M2CT-2018UGRBC/H-P8-M2
CT-2018 2018 package, top and side viewPin 1 is ringed. pin 1 DOUT (data out), pin 2 VDD (power), pin 3 DIN (data in), pin 4 GND (ground).11 DOUTdata out22 VDDpower33 DINdata in44 GNDground2.0 mm1.8 mmtop view0.8 mmside view
  • Data
  • Power
  • Ground
  • Pin 1
  • Triangle mark

Outline and pin positions checked against the manufacturer datasheet (C52191326 CT-2018URGBC/H-P8 A1 p1). Circled numbers: 1 top-left, 2 top-right, 3 bottom-right, 4 bottom-left (clockwise). Bottom-view pads 0.5 x 0.7 mm with a 1.0 mm column gap and 0.3 mm row gap (PCB land 0.6 x 0.8, 0.2 and 0.9 mm). A green triangle on the left edge marks the 1 / 4 side; the sheet does not say it is a pin-1 mark. What this means.

  1. 1 DOUT data out
  2. 2 VDD power
  3. 3 DIN data in
  4. 4 GND ground

Protocol — Chongtian M2 / M3 single-wire IC (0.3 / 0.9 us)

Timings shown from datasheet.

Chongtian M2 / M3 single-wire IC (0.3 / 0.9 us) bit timingChongtian M2 / M3 single-wire IC (0.3 / 0.9 us) bit timing: a zero bit is 300 nanoseconds high then 900 low; a one bit is 900 high then 300 low; tolerance plus or minus 50 nanoseconds; reset 200 microseconds low1 · Bit encoding, to scaleDINhighlowbit 0 period 1200 nsbit 1 period 1200 nsT0H 300 ±50 nsT1H 900 ±50 nsT0L 900 ±50 nsT1L 300 ±50 ns"0" bit"1" bit020040060080010001200140016001800200022002400time, ns± tolerance on each falling edge2 · One frame: 24 bits, most-significant bit firstDIN170110010007100110101700101100bitch 1 · 8 bitsch 2 · 8 bitsch 3 · 8 bitsChannel order not recorded for this protocol · frame = 24 × ~1200 ns ≈ 28.8 µs · example data, first bits 1 0 1 …3 · RESET / latchlast bits of frame 1first bits of frame 2LEDs latch the data they receivedRESET: DIN low ≥ 200 µs (not to scale)4 · Cascade: each DOUT feeds the next DINMCULED 1DINDOUTLED 2DINDOUTLED NDINDOUTLED 1 keeps the first 24 bits, re-shapes the signal and sends the rest out on DOUT;LED 2 keeps the next 24, and so on. The last LED's DOUT is left unconnected.
T0H 300 / T0L 900 · T1H 900 / T1L 300 ns · ±50 ns · period 1200 ns · reset 200 µs source: datasheet

Compatibility

  • protocol compatible SK6805

    Same typical bit timing (T0H 300, T0L 900, T1H 900, T1L 300 ns), 800 kbps, GRB order and a 200 us reset as the sk6805 protocol records for the OPSCO 5 mA parts, with a +/-50 ns tolerance instead of min/max windows. Chongtian never names SK6805 or any other maker; the M3 variant is also a 5 mA part, but the M2 variant drives 12 mA. source ↗

Dating evidence

Nobody announces these parts, so this records what we can actually cite rather than a release date. Library support proves only that the part existed by that date.

  • 2022-09-14 datasheet revision Chongtian CT-3210URGBC/H-P15 specification, 'Version A0, date 2022.09.14' - the earliest Chongtian sheet read ↗ day
  • 2023-01-05 datasheet revision Chongtian CT-2018URGBC/H-P8 specification, 'Version A1 issue date 2023.01.05' ↗ day
  • 2023-01-05 datasheet revision Chongtian CT-3227URGBC/H-P8 specification, 'Version A1, issue date 2023.01.05' ↗ day
  • 2026-01-23 datasheet revision Chongtian CT-2018UGRBC/H-P8-M2 specification, 'Version A2 date 2026/01/23' ↗ day

Where to buy

Stub data — a few rows so purchase links can grow later. Prices are not tracked.

Similar parts

Same protocol or package first, then the same data scheme and colour channels.

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