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Chongtian M2 / M3 single-wire IC (0.3 / 0.9 us)

1-wire RGB · Chongtian · chongtian

Channels
RGB
Bits / channel
8
Supply
3.5–5.5 V
PWM
4.5 kHz
Backup data
no
Packages
3

Chongtian does not name its IC; the designators printed on the pin-diagram art of each sheet (‘1615GRB/H-M3’, ‘0807GRB/H-M2’, ‘1209GRB/HW-MX3’) and on one cover (‘0807 RGB M3’) are used here as a handle: M3 = 5 mA, M2 = 12 mA, MX3 = 12 mA with a different timing table (see chongtian-mx3). The sheets never explain the letters. The 24-bit figure on the 2018 CT-2018URGBC/H-P8 sheet prints R7…R0 G7…G0 B7…B0 above a note that says GRB; the 1615 sheet’s figure is G7…G0 R7…R0 B7…B0. Datasheets disagree on the colour order inside the family: the CT-3227URGBC sheets say RGB (see chongtian- mx3).

Refresh & flicker

800 kbps, 256 grey levels, 24 bit per pixel sent G, R, B with the MSB first (‘Note: high bit first, in GRB order’). The 5 mA IC (labelled M3 on the sheets’ pin-diagram art ‘1615GRB/H-M3’, ‘0807 RGB M3’ on the 2018 cover) and the 12 mA IC (M2: ‘0807GRB/H-M2’) share this timing table; the M3 sheets say ‘default 5 mA per channel’, the M2 sheets ‘12 mA’. Supply 3.5-5.5 V, static 0.45 mA, DIN thresholds 3.1 V / 1.5 V, DOUT drive 14 mA, output PWM 4.5 kHz typical (the feature text says ‘port scan frequency 1.5 kHz’; datasheets disagree), DIN to DOUT delay 80 ns. Constant-current accuracy 1.5 percent in-chip and 3 percent chip-to-chip.

Timing

Chongtian M2 / M3 single-wire IC (0.3 / 0.9 us) bit timingChongtian M2 / M3 single-wire IC (0.3 / 0.9 us) bit timing: a zero bit is 300 nanoseconds high then 900 low; a one bit is 900 high then 300 low; tolerance plus or minus 50 nanoseconds; reset 200 microseconds low1 · Bit encoding, to scaleDINhighlowbit 0 period 1200 nsbit 1 period 1200 nsT0H 300 ±50 nsT1H 900 ±50 nsT0L 900 ±50 nsT1L 300 ±50 ns"0" bit"1" bit020040060080010001200140016001800200022002400time, ns± tolerance on each falling edge2 · One frame: 24 bits, most-significant bit firstDIN170110010007100110101700101100bitch 1 · 8 bitsch 2 · 8 bitsch 3 · 8 bitsChannel order not recorded for this protocol · frame = 24 × ~1200 ns ≈ 28.8 µs · example data, first bits 1 0 1 …3 · RESET / latchlast bits of frame 1first bits of frame 2LEDs latch the data they receivedRESET: DIN low ≥ 200 µs (not to scale)4 · Cascade: each DOUT feeds the next DINMCULED 1DINDOUTLED 2DINDOUTLED NDINDOUTLED 1 keeps the first 24 bits, re-shapes the signal and sends the rest out on DOUT;LED 2 keeps the next 24, and so on. The last LED's DOUT is left unconnected.
T0H 300 / T0L 900 · T1H 900 / T1L 300 ns · ±50 ns · period 1200 ns · reset 200 µs source: datasheet
SourceT0HT0LT1HT1LPeriodRateReset±
datasheet ↗ 300 ns 900 ns 900 ns 300 ns 1200 ns 833 kHz 200 µs 50 ns
Table: T code period min 1.2 us; T0H 0.3 us +/-0.05; T0L 0.9 +/-0.05; T1H 0.9 +/-0.05; T1L 0.3 +/-0.05; Trst >200 us. Note under the table: the low time of a 0 or 1 code must be below 20 us. Datasheets disagree on the reset: the table says >200 us but the data-transfer diagram on the same sheet says ‘RESET CODE >=80us’, and the 2018 functional text says ‘a low level of 80 us or more’.

Clones & compatibility

“Compatible” is never stated bare here — each relationship carries how strong the claim is, and what bites if you assume too much.

  • protocol compatible SK6805

    Same typical bit timing (T0H 300, T0L 900, T1H 900, T1L 300 ns), 800 kbps, GRB order and a 200 us reset as the sk6805 protocol records for the OPSCO 5 mA parts, with a +/-50 ns tolerance instead of min/max windows. Chongtian never names SK6805 or any other maker; the M3 variant is also a 5 mA part, but the M2 variant drives 12 mA. source ↗

Library support

Not checked against FastLED, Adafruit or WLED source.

Parts using this protocol

Dating evidence

Evidence, not a release date. A library commit proves the part existed by that date and says nothing about how long before.

  • 2022-09-14 datasheet revision Chongtian CT-3210URGBC/H-P15 specification, 'Version A0, date 2022.09.14' - the earliest Chongtian sheet read ↗ day