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3.2 × 1.0 mm 4 pins top-emitting

CT-3210URGBC/H-P15

3210 · smd · Chongtian M2 / M3 single-wire IC (0.3 / 0.9 us) · Chongtian

1-wire RGB 3.5–5.5 V active

Also sold as CT-3210, 1204 RGB

At a glance

Colour
RGB8 bits per channel
Data
1-wiretimed pulses on one line
Supply
3.5–5.5 Vno backup data line
Size
3.2 × 1.0 × 1.5 mm4 pins · top
Max current
36 mA12 mA per channel
PWM
4.5 kHzreset 200 µs
Library support
FastLED WLED Adafruit

3.2 x 1.0 mm with a 1.5 mm tall dome (1.5 mm is the end-view width; the sheet calls the part ‘1204’ in its title and uses the 3210 code in the part number). Pin 1 is DIN here, unlike the DOUT pin 1 of the other Chongtian packages. Timing is the chongtian-m table. LCSC stock 830 on 2026-10-15.

Variants

One row per orderable SKU. Everything not listed is inherited from the part above.

Order codeFaceLensWhite PinsSiliconStatusFirst seenDatasheet
CT-3210URGBC/H-P15 — clear — 4 — active 2022-09-14 A0
LCSC C52191337, stock 830.

Pinout

CT-3210URGBC/H-P15
CT-3210URGBC/H-P15 3210 package, top and side viewPin 1 is ringed. pin 1 DIN (data in), pin 2 DOUT (data out), pin 3 VDD (power), pin 4 GND (ground).11 DINdata in22 DOUTdata out33 VDDpower44 GNDground3.2 mm1.0 mmtop view1.5 mmside view
  • Data
  • Power
  • Ground
  • Pin 1

Outline and pin positions checked against the manufacturer datasheet (C52191337 CT-3210URGBC/H-P15 A0 p1). Top view: 3 VDD top-left, 4 GND top-right, 2 DOUT bottom-left, 1 DIN bottom-right, so numbering runs clockwise from the bottom-right. Four corner pads on the two 3.2 mm ends; pad sizes approximate (0.55 / 0.4 / 0.37 mm callouts). A green triangle at the right end is the only mark. Same pad pattern as the OPSCO SK6805-EC3210R and Inolux PI3210. What this means.

  1. 1 DIN data in
  2. 2 DOUT data out
  3. 3 VDD power
  4. 4 GND ground

Protocol — Chongtian M2 / M3 single-wire IC (0.3 / 0.9 us)

Timings shown from datasheet.

Chongtian M2 / M3 single-wire IC (0.3 / 0.9 us) bit timingChongtian M2 / M3 single-wire IC (0.3 / 0.9 us) bit timing: a zero bit is 300 nanoseconds high then 900 low; a one bit is 900 high then 300 low; tolerance plus or minus 50 nanoseconds; reset 200 microseconds low1 · Bit encoding, to scaleDINhighlowbit 0 period 1200 nsbit 1 period 1200 nsT0H 300 ±50 nsT1H 900 ±50 nsT0L 900 ±50 nsT1L 300 ±50 ns"0" bit"1" bit020040060080010001200140016001800200022002400time, ns± tolerance on each falling edge2 · One frame: 24 bits, most-significant bit firstDIN170110010007100110101700101100bitch 1 · 8 bitsch 2 · 8 bitsch 3 · 8 bitsChannel order not recorded for this protocol · frame = 24 × ~1200 ns ≈ 28.8 µs · example data, first bits 1 0 1 …3 · RESET / latchlast bits of frame 1first bits of frame 2LEDs latch the data they receivedRESET: DIN low ≥ 200 µs (not to scale)4 · Cascade: each DOUT feeds the next DINMCULED 1DINDOUTLED 2DINDOUTLED NDINDOUTLED 1 keeps the first 24 bits, re-shapes the signal and sends the rest out on DOUT;LED 2 keeps the next 24, and so on. The last LED's DOUT is left unconnected.
T0H 300 / T0L 900 · T1H 900 / T1L 300 ns · ±50 ns · period 1200 ns · reset 200 µs source: datasheet

Compatibility

  • protocol compatible SK6805

    Same typical bit timing (T0H 300, T0L 900, T1H 900, T1L 300 ns), 800 kbps, GRB order and a 200 us reset as the sk6805 protocol records for the OPSCO 5 mA parts, with a +/-50 ns tolerance instead of min/max windows. Chongtian never names SK6805 or any other maker; the M3 variant is also a 5 mA part, but the M2 variant drives 12 mA. source ↗

Dating evidence

Nobody announces these parts, so this records what we can actually cite rather than a release date. Library support proves only that the part existed by that date.

  • 2022-09-14 datasheet revision Chongtian CT-3210URGBC/H-P15 specification, 'Version A0, date 2022.09.14' - the earliest Chongtian sheet read ↗ day

Where to buy

Stub data — a few rows so purchase links can grow later. Prices are not tracked.

Similar parts

Same protocol or package first, then the same data scheme and colour channels.

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