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5.0 × 5.0 mm 6 pins top-emitting

WL-ICLED 1315050930246

5050 · smd · WL-ICLED (dual-wire) · Wurth Elektronik

SPI RGB 3.3–5.5 V active

Also sold as 1315050930246

At a glance

Colour
RGB8 bits per channel
Data
SPIclock + data, timing-tolerant
Supply
3.3–5.5 Vno backup data line
Size
5.0 × 5.0 × 1.6 mm6 pins · top
Max current
65 mAper-channel not recorded
PWM
20 kHzno reset period
Library support
FastLED WLED Adafruit

A clocked 5050 with an APA102-like frame. Compare the pinout against the SK9822 and APA102C 5050s before laying out a board: the pad positions are the same six, but the signals are in a different order.

Variants

One row per orderable SKU. Everything not listed is inherited from the part above.

Order codeFaceLensWhite PinsSiliconStatusFirst seenDatasheet
1315050930246 white clear — 6 — active 2024-07-05 001.000
White housing, water-clear lens (“PLCC6 Top view”).

Pinout

1315050930246
WL-ICLED 1315050930246 5050 package, top and side viewPin 1 is ringed. pin 1 DIN (data in), pin 2 CIN (clock in), pin 3 VSS (ground), pin 4 VDD (power), pin 5 COUT (clock out), pin 6 DOUT (data out).11 DINdata in22 CINclock in33 VSSground44 VDDpower55 COUTclock out66 DOUTdata out5.4 mm overall5.0 mmtop view1.6 mmside view
  • Data
  • Clock
  • Ground
  • Power
  • Pin 1
  • Cut corner

Outline and pin positions checked against the manufacturer datasheet (Wurth 1315050930246 sheet p1: pin 1 at the marked top-left corner, 1-2-3 down the left, 4-5-6 up the right). Pad layout matches the SK9822 5050; the pin assignment does not. What this means.

  1. 1 DIN data in
  2. 2 CIN clock in
  3. 3 VSS ground
  4. 4 VDD power
  5. 5 COUT clock out
  6. 6 DOUT data out

Protocol — WL-ICLED (dual-wire)

This is an SPI part: the clock is explicit, so there is no fixed bit period. The frame layout is shown below.

WL-ICLED (dual-wire) SPI frameWL-ICLED (dual-wire) clocked frame: start frame, one 32-bit LED frame per pixel with brightness and colour bytes, and an end frame, plus data and clock waveforms1 · Frame stream (data clocked on CLK)Start frame32 × 0LED 132 bitsLED 232 bits…LED N32 bitsEnd frameclock ≥ N/2 edgeseach LED forwards what it does not keep on DO / CO2 · One LED frame: 32 bits, MSB first111brightch 1 8ch 2 8ch 3 83 marker bits (111), 5-bit global brightness 0–31, then 8-bit channels3 · DATA and CLK, first 8 bits of an LED frameDATACLK11110010111 markerbrightness bits 4..0data changes while CLK is low,LED samples on the rising edgeno fixed bit period: clock rateis set by the host
Frame layout: APA102-family 32-bit LED frames convention, see the protocol notes for end-frame differences

Compatibility

  • protocol compatible APA102

    The frame layout reads like the APA102's: 32-bit zero start frame, 3 flag bits, 5-bit global brightness, blue-green-red 8-bit values, N/2 end bits. The differences on paper are the flag decoding (0b101 puts the LED to sleep) and the 300 ohm series resistors on both lines in the reference circuit. Nothing here has been run against an APA102 driver. source ↗

Dating evidence

Nobody announces these parts, so this records what we can actually cite rather than a release date. Library support proves only that the part existed by that date.

  • 2024-07-05 datasheet revision Wurth WL-ICLED 1315050930246 and 1311610030140 datasheets, revision 001.000 ↗ day

Similar parts

Same protocol or package first, then the same data scheme and colour channels.

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